radv: fix non-0 based layer clears.

[mesa.git] / src / amd / vulkan / radv_private.h

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index a8bc5c96586567ea5481ec2195c13dfc5b984455..8cd5ec00463e58b53d2ffb838334cc756f6d617a 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -547,6 +547,8 @@ struct radv_device {
 
        /* Backup in-memory cache to be used if the app doesn't provide one */
        struct radv_pipeline_cache *                mem_cache;
+
+       uint32_t image_mrt_offset_counter;
 };
 
 struct radv_device_memory {
@@ -869,7 +871,7 @@ void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
                            bool is_mec,
                            enum radv_cmd_flush_bits flush_bits);
 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
-void si_emit_set_pred(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
+void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
                           uint64_t src_va, uint64_t dest_va,
                           uint64_t size);
@@ -912,6 +914,9 @@ void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
                               struct radv_image *image,
                               int idx,
                               uint32_t color_values[2]);
+void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
+                                      struct radv_image *image,
+                                      bool value);
 void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
                      struct radeon_winsys_bo *bo,
                      uint64_t offset, uint64_t size, uint32_t value);
@@ -1205,6 +1210,8 @@ struct radv_image {
        bool exclusive;
        unsigned queue_family_mask;
 
+       bool shareable;
+
        /* Set when bound */
        struct radeon_winsys_bo *bo;
        VkDeviceSize offset;
@@ -1215,6 +1222,7 @@ struct radv_image {
        struct radv_fmask_info fmask;
        struct radv_cmask_info cmask;
        uint32_t clear_value_offset;
+       uint32_t dcc_pred_offset;
 };
 
 /* Whether the image has a htile that is known consistent with the contents of
@@ -1462,6 +1470,20 @@ struct radv_query_pool {
        uint32_t pipeline_stats_mask;
 };
 
+struct radv_semaphore {
+       /* use a winsys sem for non-exportable */
+       struct radeon_winsys_sem *sem;
+       uint32_t syncobj;
+       uint32_t temp_syncobj;
+};
+
+VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
+                            int num_wait_sems,
+                            const VkSemaphore *wait_sems,
+                            int num_signal_sems,
+                            const VkSemaphore *signal_sems);
+void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
+
 void
 radv_update_descriptor_sets(struct radv_device *device,
                             struct radv_cmd_buffer *cmd_buffer,
@@ -1555,6 +1577,6 @@ RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
-RADV_DEFINE_NONDISP_HANDLE_CASTS(radeon_winsys_sem, VkSemaphore)
+RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
 
 #endif /* RADV_PRIVATE_H */