#define RADV_MAX_QUEUE_FAMILIES 3
+struct radv_deferred_queue_submission;
+
enum ring_type radv_queue_family_to_ring(int f);
struct radv_queue {
struct list_head pending_submissions;
pthread_mutex_t pending_mutex;
+
+ pthread_mutex_t thread_mutex;
+ pthread_cond_t thread_cond;
+ struct radv_deferred_queue_submission *thread_submission;
+ pthread_t submission_thread;
+ bool thread_exit;
+ bool thread_running;
};
struct radv_bo_list {
struct radv_vertex_binding {
struct radv_buffer * buffer;
VkDeviceSize offset;
+ VkDeviceSize size;
+ VkDeviceSize stride;
};
struct radv_streamout_binding {
uint32_t back;
} stencil_write_mask;
+ struct {
+ struct {
+ VkStencilOp fail_op;
+ VkStencilOp pass_op;
+ VkStencilOp depth_fail_op;
+ VkCompareOp compare_op;
+ } front;
+
+ struct {
+ VkStencilOp fail_op;
+ VkStencilOp pass_op;
+ VkStencilOp depth_fail_op;
+ VkCompareOp compare_op;
+ } back;
+ } stencil_op;
+
struct {
uint32_t front;
uint32_t back;
uint32_t factor;
uint16_t pattern;
} line_stipple;
+
+ VkCullModeFlags cull_mode;
+ VkFrontFace front_face;
+ unsigned primitive_topology;
+
+ bool depth_test_enable;
+ bool depth_write_enable;
+ VkCompareOp depth_compare_op;
+ bool depth_bounds_test_enable;
+ bool stencil_test_enable;
};
extern const struct radv_dynamic_state default_dynamic_state;
uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
bool instanced_draw, bool indirect_draw,
bool count_from_stream_output,
- uint32_t draw_vertex_count);
+ uint32_t draw_vertex_count,
+ unsigned topology);
void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
enum chip_class chip_class,
bool is_mec,
bool radv_get_memory_fd(struct radv_device *device,
struct radv_device_memory *memory,
int *pFD);
+void radv_free_memory(struct radv_device *device,
+ const VkAllocationCallbacks* pAllocator,
+ struct radv_device_memory *mem);
static inline void
radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
uint8_t incr;
};
-struct radv_vertex_elements_info {
- uint32_t format_size[MAX_VERTEX_ATTRIBS];
-};
-
struct radv_ia_multi_vgt_param_helpers {
uint32_t base;
bool partial_es_wave;
uint32_t ctx_cs_hash;
struct radeon_cmdbuf ctx_cs;
- struct radv_vertex_elements_info vertex_elements;
-
uint32_t binding_stride[MAX_VBS];
uint8_t num_vertex_bindings;
bool can_use_guardband;
uint32_t needed_dynamic_state;
bool disable_out_of_order_rast_for_occlusion;
- uint8_t topology;
unsigned tess_patch_control_points;
+ unsigned pa_su_sc_mode_cntl;
+ unsigned db_depth_control;
+ bool uses_dynamic_stride;
/* Used for rbplus */
uint32_t col_format;
uint32_t cb_target_mask;
- bool is_dual_src;
} graphics;
};
RADV_SEMAPHORE_NONE,
RADV_SEMAPHORE_WINSYS,
RADV_SEMAPHORE_SYNCOBJ,
+ RADV_SEMAPHORE_TIMELINE_SYNCOBJ,
RADV_SEMAPHORE_TIMELINE,
} radv_semaphore_kind;
struct list_head waiters;
};
+struct radv_timeline_syncobj {
+ /* Keep syncobj first, so common-code can just handle this as
+ * non-timeline syncobj. */
+ uint32_t syncobj;
+ uint64_t max_point; /* max submitted point. */
+};
+
struct radv_semaphore_part {
radv_semaphore_kind kind;
union {
uint32_t syncobj;
struct radeon_winsys_sem *ws_sem;
struct radv_timeline timeline;
+ struct radv_timeline_syncobj timeline_syncobj;
};
};
struct radv_image *image,
const VkImageSubresourceRange *range);
+typedef enum {
+ RADV_FENCE_NONE,
+ RADV_FENCE_WINSYS,
+ RADV_FENCE_SYNCOBJ,
+ RADV_FENCE_WSI,
+} radv_fence_kind;
+
+struct radv_fence_part {
+ radv_fence_kind kind;
+
+ union {
+ /* AMDGPU winsys fence. */
+ struct radeon_winsys_fence *fence;
+
+ /* DRM syncobj handle for syncobj-based fences. */
+ uint32_t syncobj;
+
+ /* WSI fence. */
+ struct wsi_fence *fence_wsi;
+ };
+};
+
struct radv_fence {
struct vk_object_base base;
- struct radeon_winsys_fence *fence;
- struct wsi_fence *fence_wsi;
-
- uint32_t syncobj;
- uint32_t temp_syncobj;
+ struct radv_fence_part permanent;
+ struct radv_fence_part temporary;
};
/* radv_nir_to_llvm.c */
const VkRenderPassBeginInfo *pRenderPassBegin);
void radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer);
+static inline uint32_t si_translate_prim(unsigned topology)
+{
+ switch (topology) {
+ case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
+ return V_008958_DI_PT_POINTLIST;
+ case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
+ return V_008958_DI_PT_LINELIST;
+ case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
+ return V_008958_DI_PT_LINESTRIP;
+ case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
+ return V_008958_DI_PT_TRILIST;
+ case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
+ return V_008958_DI_PT_TRISTRIP;
+ case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
+ return V_008958_DI_PT_TRIFAN;
+ case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
+ return V_008958_DI_PT_LINELIST_ADJ;
+ case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
+ return V_008958_DI_PT_LINESTRIP_ADJ;
+ case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
+ return V_008958_DI_PT_TRILIST_ADJ;
+ case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
+ return V_008958_DI_PT_TRISTRIP_ADJ;
+ case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
+ return V_008958_DI_PT_PATCH;
+ default:
+ assert(0);
+ return 0;
+ }
+}
+
+static inline uint32_t si_translate_stencil_op(enum VkStencilOp op)
+{
+ switch (op) {
+ case VK_STENCIL_OP_KEEP:
+ return V_02842C_STENCIL_KEEP;
+ case VK_STENCIL_OP_ZERO:
+ return V_02842C_STENCIL_ZERO;
+ case VK_STENCIL_OP_REPLACE:
+ return V_02842C_STENCIL_REPLACE_TEST;
+ case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
+ return V_02842C_STENCIL_ADD_CLAMP;
+ case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
+ return V_02842C_STENCIL_SUB_CLAMP;
+ case VK_STENCIL_OP_INVERT:
+ return V_02842C_STENCIL_INVERT;
+ case VK_STENCIL_OP_INCREMENT_AND_WRAP:
+ return V_02842C_STENCIL_ADD_WRAP;
+ case VK_STENCIL_OP_DECREMENT_AND_WRAP:
+ return V_02842C_STENCIL_SUB_WRAP;
+ default:
+ return 0;
+ }
+}
+
#define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
\
static inline struct __radv_type * \
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