amd/common: add declare_vs_input_vgprs() helper

[mesa.git] / src / amd / vulkan / radv_private.h

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 16afd6d692189d7f08f1587153888a53d1de197f..acc4ed4dc92257a6292f25115af0f42d2d14519e 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -353,6 +353,22 @@ radv_pipeline_cache_insert_shaders(struct radv_device *device,
                                   const void *const *codes,
                                   const unsigned *code_sizes);
 
+enum radv_blit_ds_layout {
+       RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
+       RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
+       RADV_BLIT_DS_LAYOUT_COUNT,
+};
+
+static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
+{
+       return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
+}
+
+static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
+{
+       return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
+}
+
 struct radv_meta_state {
        VkAllocationCallbacks alloc;
 
@@ -385,12 +401,12 @@ struct radv_meta_state {
                /** Pipeline that blits from a 3D image. */
                VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
 
-               VkRenderPass depth_only_rp;
+               VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
                VkPipeline depth_only_1d_pipeline;
                VkPipeline depth_only_2d_pipeline;
                VkPipeline depth_only_3d_pipeline;
 
-               VkRenderPass stencil_only_rp;
+               VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
                VkPipeline stencil_only_1d_pipeline;
                VkPipeline stencil_only_2d_pipeline;
                VkPipeline stencil_only_3d_pipeline;
@@ -401,21 +417,22 @@ struct radv_meta_state {
        struct {
                VkRenderPass render_passes[NUM_META_FS_KEYS];
 
-               VkPipelineLayout p_layouts[2];
-               VkDescriptorSetLayout ds_layouts[2];
-               VkPipeline pipelines[2][NUM_META_FS_KEYS];
+               VkPipelineLayout p_layouts[3];
+               VkDescriptorSetLayout ds_layouts[3];
+               VkPipeline pipelines[3][NUM_META_FS_KEYS];
 
-               VkRenderPass depth_only_rp;
-               VkPipeline depth_only_pipeline[2];
+               VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
+               VkPipeline depth_only_pipeline[3];
 
-               VkRenderPass stencil_only_rp;
-               VkPipeline stencil_only_pipeline[2];
+               VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
+               VkPipeline stencil_only_pipeline[3];
        } blit2d;
 
        struct {
                VkPipelineLayout                          img_p_layout;
                VkDescriptorSetLayout                     img_ds_layout;
                VkPipeline pipeline;
+               VkPipeline pipeline_3d;
        } itob;
        struct {
                VkPipelineLayout                          img_p_layout;
@@ -434,6 +451,7 @@ struct radv_meta_state {
        } cleari;
 
        struct {
+               VkPipelineLayout                          p_layout;
                VkPipeline                                pipeline;
                VkRenderPass                              pass;
        } resolve;
@@ -459,12 +477,14 @@ struct radv_meta_state {
        } resolve_fragment;
 
        struct {
+               VkPipelineLayout                          p_layout;
                VkPipeline                                decompress_pipeline;
                VkPipeline                                resummarize_pipeline;
                VkRenderPass                              pass;
        } depth_decomp[1 + MAX_SAMPLES_LOG2];
 
        struct {
+               VkPipelineLayout                          p_layout;
                VkPipeline                                cmask_eliminate_pipeline;
                VkPipeline                                fmask_decompress_pipeline;
                VkRenderPass                              pass;
@@ -542,6 +562,7 @@ struct radv_device {
        bool dfsm_allowed;
        uint32_t tess_offchip_block_dw_size;
        uint32_t scratch_waves;
+       uint32_t dispatch_initiator;
 
        uint32_t gs_table_depth;
 
@@ -1255,7 +1276,6 @@ struct radv_cmask_info {
        uint64_t size;
        unsigned alignment;
        unsigned slice_tile_max;
-       unsigned base_address_reg;
 };
 
 struct radv_image {
@@ -1557,7 +1577,8 @@ VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
                             int num_wait_sems,
                             const VkSemaphore *wait_sems,
                             int num_signal_sems,
-                            const VkSemaphore *signal_sems);
+                            const VkSemaphore *signal_sems,
+                            VkFence fence);
 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
 
 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
@@ -1596,6 +1617,9 @@ struct radv_fence {
        struct radeon_winsys_fence *fence;
        bool submitted;
        bool signalled;
+
+       uint32_t syncobj;
+       uint32_t temp_syncobj;
 };
 
 struct radeon_winsys_sem;