radv: do not pass all compiler options to the shader info pass

[mesa.git] / src / amd / vulkan / radv_private.h

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index fbc4542cd729dbf70948937bdeee1a64715f90a8..bf62ccc9c1d8bfbed8acb34e037da67b7ef03721 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -280,28 +280,14 @@ struct radv_physical_device {
        int master_fd;
        struct wsi_device                       wsi_device;
 
-       bool has_rbplus; /* if RB+ register exist */
-       bool rbplus_allowed; /* if RB+ is allowed */
-       bool has_clear_state;
-       bool cpdma_prefetch_writes_memory;
-       bool has_scissor_bug;
-       bool has_tc_compat_zrange_bug;
-
-       bool has_out_of_order_rast;
        bool out_of_order_rast_allowed;
 
        /* Whether DCC should be enabled for MSAA textures. */
        bool dcc_msaa_allowed;
 
-       /* Whether LOAD_CONTEXT_REG packets are supported. */
-       bool has_load_ctx_reg_pkt;
-
        /* Whether to enable the AMD_shader_ballot extension */
        bool use_shader_ballot;
 
-       /* Whether DISABLE_CONSTANT_ENCODE_REG is supported. */
-       bool has_dcc_constant_encode;
-
        /* Number of threads per wave. */
        uint8_t ps_wave_size;
        uint8_t cs_wave_size;
@@ -705,7 +691,6 @@ struct radv_device {
        struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
 
        bool always_use_syncobj;
-       bool has_distributed_tess;
        bool pbb_allowed;
        bool dfsm_allowed;
        uint32_t tess_offchip_block_dw_size;
@@ -1331,7 +1316,7 @@ unsigned radv_get_default_max_sample_dist(int log_samples);
 void radv_device_init_msaa(struct radv_device *device);
 
 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
-                                  struct radv_image *image,
+                                  const struct radv_image_view *iview,
                                   VkClearDepthStencilValue ds_clear_value,
                                   VkImageAspectFlags aspects);
 
@@ -1423,6 +1408,9 @@ struct radv_shader_module;
 #define RADV_HASH_SHADER_SISCHED             (1 << 1)
 #define RADV_HASH_SHADER_UNSAFE_MATH         (1 << 2)
 #define RADV_HASH_SHADER_NO_NGG              (1 << 3)
+#define RADV_HASH_SHADER_CS_WAVE32           (1 << 4)
+#define RADV_HASH_SHADER_PS_WAVE32           (1 << 5)
+#define RADV_HASH_SHADER_GE_WAVE32           (1 << 6)
 
 void
 radv_hash_shaders(unsigned char *hash,
@@ -1685,7 +1673,8 @@ bool radv_layout_can_fast_clear(const struct radv_image *image,
                                bool in_render_loop,
                                unsigned queue_mask);
 
-bool radv_layout_dcc_compressed(const struct radv_image *image,
+bool radv_layout_dcc_compressed(const struct radv_device *device,
+                               const struct radv_image *image,
                                VkImageLayout layout,
                                bool in_render_loop,
                                unsigned queue_mask);
@@ -1801,6 +1790,24 @@ radv_image_get_dcc_pred_va(const struct radv_image *image,
        return va;
 }
 
+static inline uint64_t
+radv_get_tc_compat_zrange_va(const struct radv_image *image,
+                            uint32_t base_level)
+{
+       uint64_t va = radv_buffer_get_va(image->bo);
+       va += image->offset + image->tc_compat_zrange_offset + base_level * 4;
+       return va;
+}
+
+static inline uint64_t
+radv_get_ds_clear_value_va(const struct radv_image *image,
+                          uint32_t base_level)
+{
+       uint64_t va = radv_buffer_get_va(image->bo);
+       va += image->offset + image->clear_value_offset + base_level * 8;
+       return va;
+}
+
 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
 
 static inline uint32_t
@@ -1883,6 +1890,7 @@ radv_image_from_gralloc(VkDevice device_h,
                        VkImage *out_image_h);
 
 struct radv_image_view_extra_create_info {
+       bool disable_compression;
 };
 
 void radv_image_view_init(struct radv_image_view *view,
@@ -2099,18 +2107,18 @@ struct radv_fence {
 };
 
 /* radv_nir_to_llvm.c */
-struct radv_shader_variant_info;
+struct radv_shader_info;
 struct radv_nir_compiler_options;
 
 void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
                                 struct nir_shader *geom_shader,
                                 struct radv_shader_binary **rbinary,
-                                struct radv_shader_variant_info *shader_info,
+                                struct radv_shader_info *info,
                                 const struct radv_nir_compiler_options *option);
 
 void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
                             struct radv_shader_binary **rbinary,
-                            struct radv_shader_variant_info *shader_info,
+                            struct radv_shader_info *info,
                             struct nir_shader *const *nir,
                             int nir_count,
                             const struct radv_nir_compiler_options *options);
@@ -2121,9 +2129,11 @@ unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
 
 /* radv_shader_info.h */
 struct radv_shader_info;
+struct radv_shader_variant_key;
 
 void radv_nir_shader_info_pass(const struct nir_shader *nir,
-                              const struct radv_nir_compiler_options *options,
+                              const struct radv_pipeline_layout *layout,
+                              const struct radv_shader_variant_key *key,
                               struct radv_shader_info *info);
 
 void radv_nir_shader_info_init(struct radv_shader_info *info);