radv: enable TC-compat HTILE for 16-bit depth surfaces on GFX8

[mesa.git] / src / amd / vulkan / radv_private.h

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 797bc8cd0ae99c5bc1f5b0d1b3b0b33223260dc6..ce2e487bdb5b61e8d36f3720d1a6b8f27bfbd1ab 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -87,7 +87,9 @@ typedef uint32_t xcb_window_t;
 #define MAX_DISCARD_RECTANGLES 4
 #define MAX_PUSH_CONSTANTS_SIZE 128
 #define MAX_PUSH_DESCRIPTORS 32
-#define MAX_DYNAMIC_BUFFERS 16
+#define MAX_DYNAMIC_UNIFORM_BUFFERS 16
+#define MAX_DYNAMIC_STORAGE_BUFFERS 8
+#define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
 #define MAX_SAMPLES_LOG2 4
 #define NUM_META_FS_KEYS 13
 #define RADV_MAX_DRM_DEVICES 8
@@ -95,6 +97,12 @@ typedef uint32_t xcb_window_t;
 
 #define NUM_DEPTH_CLEAR_PIPELINES 3
 
+/*
+ * This is the point we switch from using CP to compute shader
+ * for certain buffer operations.
+ */
+#define RADV_BUFFER_OPS_CS_THRESHOLD 4096
+
 enum radv_mem_heap {
        RADV_MEM_HEAP_VRAM,
        RADV_MEM_HEAP_VRAM_CPU_ACCESS,
@@ -565,6 +573,7 @@ struct radv_queue {
        enum radeon_ctx_priority                     priority;
        uint32_t queue_family_index;
        int queue_idx;
+       VkDeviceQueueCreateFlags flags;
 
        uint32_t scratch_size;
        uint32_t compute_scratch_size;
@@ -736,7 +745,6 @@ struct radv_descriptor_update_template {
 };
 
 struct radv_buffer {
-       struct radv_device *                          device;
        VkDeviceSize                                 size;
 
        VkBufferUsageFlags                           usage;
@@ -1004,6 +1012,11 @@ struct radv_cmd_buffer {
        uint32_t gfx9_fence_offset;
        struct radeon_winsys_bo *gfx9_fence_bo;
        uint32_t gfx9_fence_idx;
+
+       /**
+        * Whether a query pool has been resetted and we have to flush caches.
+        */
+       bool pending_reset_query;
 };
 
 struct radv_image;
@@ -1194,7 +1207,6 @@ struct radv_pipeline {
 
        struct radv_pipeline_layout *                 layout;
 
-       bool                                         needs_data_cache;
        bool                                         need_indirect_descriptor_sets;
        struct radv_shader_variant *                 shaders[MESA_SHADER_STAGES];
        struct radv_shader_variant *gs_copy_shader;
@@ -1237,9 +1249,9 @@ static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
        return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
 }
 
-struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
-                                              gl_shader_stage stage,
-                                              int idx);
+struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
+                                                gl_shader_stage stage,
+                                                int idx);
 
 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
 
@@ -1602,6 +1614,7 @@ struct radv_query_pool {
        struct radeon_winsys_bo *bo;
        uint32_t stride;
        uint32_t availability_offset;
+       uint64_t size;
        char *ptr;
        VkQueryType type;
        uint32_t pipeline_stats_mask;
@@ -1664,6 +1677,32 @@ struct radv_fence {
        uint32_t temp_syncobj;
 };
 
+/* radv_nir_to_llvm.c */
+struct radv_shader_variant_info;
+struct radv_nir_compiler_options;
+
+void radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
+                                struct nir_shader *geom_shader,
+                                struct ac_shader_binary *binary,
+                                struct ac_shader_config *config,
+                                struct radv_shader_variant_info *shader_info,
+                                const struct radv_nir_compiler_options *option);
+
+void radv_compile_nir_shader(LLVMTargetMachineRef tm,
+                            struct ac_shader_binary *binary,
+                            struct ac_shader_config *config,
+                            struct radv_shader_variant_info *shader_info,
+                            struct nir_shader *const *nir,
+                            int nir_count,
+                            const struct radv_nir_compiler_options *options);
+
+/* radv_shader_info.h */
+struct radv_shader_info;
+
+void radv_nir_shader_info_pass(const struct nir_shader *nir,
+                              const struct radv_nir_compiler_options *options,
+                              struct radv_shader_info *info);
+
 struct radeon_winsys_sem;
 
 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType)                \