#include "util/list.h"
#include "main/macros.h"
#include "vk_alloc.h"
+#include "vk_debug_report.h"
#include "radv_radeon_winsys.h"
#include "ac_binary.h"
#define MAX_RTS 8
#define MAX_VIEWPORTS 16
#define MAX_SCISSORS 16
+#define MAX_DISCARD_RECTANGLES 4
#define MAX_PUSH_CONSTANTS_SIZE 128
#define MAX_PUSH_DESCRIPTORS 32
#define MAX_DYNAMIC_BUFFERS 16
bool has_rbplus; /* if RB+ register exist */
bool rbplus_allowed; /* if RB+ is allowed */
bool has_clear_state;
+ bool cpdma_prefetch_writes_memory;
+ bool has_scissor_bug;
/* This is the drivers on-disk cache used as a fallback as opposed to
* the pipeline cache defined by apps.
uint64_t debug_flags;
uint64_t perftest_flags;
+
+ struct vk_debug_report_instance debug_report_callbacks;
};
VkResult radv_init_wsi(struct radv_physical_device *physical_device);
const void *const *codes,
const unsigned *code_sizes);
+enum radv_blit_ds_layout {
+ RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
+ RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
+ RADV_BLIT_DS_LAYOUT_COUNT,
+};
+
+static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
+{
+ return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
+}
+
+static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
+{
+ return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
+}
+
+enum radv_meta_dst_layout {
+ RADV_META_DST_LAYOUT_GENERAL,
+ RADV_META_DST_LAYOUT_OPTIMAL,
+ RADV_META_DST_LAYOUT_COUNT,
+};
+
+static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
+{
+ return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
+}
+
+static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
+{
+ return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
+}
+
struct radv_meta_state {
VkAllocationCallbacks alloc;
VkPipelineLayout clear_color_p_layout;
VkPipelineLayout clear_depth_p_layout;
struct {
- VkRenderPass render_pass[NUM_META_FS_KEYS];
+ VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
/** Pipeline that blits from a 1D image. */
VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
/** Pipeline that blits from a 3D image. */
VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
- VkRenderPass depth_only_rp;
+ VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
VkPipeline depth_only_1d_pipeline;
VkPipeline depth_only_2d_pipeline;
VkPipeline depth_only_3d_pipeline;
- VkRenderPass stencil_only_rp;
+ VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
VkPipeline stencil_only_1d_pipeline;
VkPipeline stencil_only_2d_pipeline;
VkPipeline stencil_only_3d_pipeline;
} blit;
struct {
- VkRenderPass render_passes[NUM_META_FS_KEYS];
+ VkRenderPass render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
- VkPipelineLayout p_layouts[2];
- VkDescriptorSetLayout ds_layouts[2];
- VkPipeline pipelines[2][NUM_META_FS_KEYS];
+ VkPipelineLayout p_layouts[3];
+ VkDescriptorSetLayout ds_layouts[3];
+ VkPipeline pipelines[3][NUM_META_FS_KEYS];
- VkRenderPass depth_only_rp;
- VkPipeline depth_only_pipeline[2];
+ VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
+ VkPipeline depth_only_pipeline[3];
- VkRenderPass stencil_only_rp;
- VkPipeline stencil_only_pipeline[2];
+ VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
+ VkPipeline stencil_only_pipeline[3];
} blit2d;
struct {
VkPipelineLayout img_p_layout;
VkDescriptorSetLayout img_ds_layout;
VkPipeline pipeline;
+ VkPipeline pipeline_3d;
} itob;
struct {
VkPipelineLayout img_p_layout;
VkDescriptorSetLayout img_ds_layout;
VkPipeline pipeline;
+ VkPipeline pipeline_3d;
} btoi;
struct {
VkPipelineLayout img_p_layout;
VkDescriptorSetLayout img_ds_layout;
VkPipeline pipeline;
+ VkPipeline pipeline_3d;
} itoi;
struct {
VkPipelineLayout img_p_layout;
VkDescriptorSetLayout img_ds_layout;
VkPipeline pipeline;
+ VkPipeline pipeline_3d;
} cleari;
struct {
+ VkPipelineLayout p_layout;
VkPipeline pipeline;
VkRenderPass pass;
} resolve;
VkPipelineLayout p_layout;
struct {
- VkRenderPass render_pass[NUM_META_FS_KEYS];
+ VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
VkPipeline pipeline[NUM_META_FS_KEYS];
} rc[MAX_SAMPLES_LOG2];
} resolve_fragment;
struct {
+ VkPipelineLayout p_layout;
VkPipeline decompress_pipeline;
VkPipeline resummarize_pipeline;
VkRenderPass pass;
} depth_decomp[1 + MAX_SAMPLES_LOG2];
struct {
+ VkPipelineLayout p_layout;
VkPipeline cmask_eliminate_pipeline;
VkPipeline fmask_decompress_pipeline;
+ VkPipeline dcc_decompress_pipeline;
VkRenderPass pass;
+
+ VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
+ VkPipelineLayout dcc_decompress_compute_p_layout;
+ VkPipeline dcc_decompress_compute_pipeline;
} fast_clear_flush;
struct {
bool llvm_supports_spill;
bool has_distributed_tess;
+ bool pbb_allowed;
bool dfsm_allowed;
uint32_t tess_offchip_block_dw_size;
uint32_t scratch_waves;
bool shareable;
};
+enum radv_dynamic_state_bits {
+ RADV_DYNAMIC_VIEWPORT = 1 << 0,
+ RADV_DYNAMIC_SCISSOR = 1 << 1,
+ RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
+ RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
+ RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
+ RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
+ RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
+ RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
+ RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
+ RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
+ RADV_DYNAMIC_ALL = (1 << 10) - 1,
+};
enum radv_cmd_dirty_bits {
- RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
- RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
- RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
- RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
- RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
- RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
- RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
- RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
- RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
- RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
- RADV_CMD_DIRTY_PIPELINE = 1 << 9,
- RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
- RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 11,
- RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 12,
+ /* Keep the dynamic state dirty bits in sync with
+ * enum radv_dynamic_state_bits */
+ RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
+ RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
+ RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
+ RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
+ RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
+ RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
+ RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
+ RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
+ RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
+ RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
+ RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
+ RADV_CMD_DIRTY_PIPELINE = 1 << 10,
+ RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
+ RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
+ RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
};
enum radv_cmd_flush_bits {
VkRect2D scissors[MAX_SCISSORS];
};
+struct radv_discard_rectangle_state {
+ uint32_t count;
+ VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
+};
+
struct radv_dynamic_state {
/**
* Bitmask of (1 << VK_DYNAMIC_STATE_*).
uint32_t front;
uint32_t back;
} stencil_reference;
+
+ struct radv_discard_rectangle_state discard_rectangle;
};
extern const struct radv_dynamic_state default_dynamic_state;
uint32_t valid_descriptors;
uint32_t trace_id;
uint32_t last_ia_multi_vgt_param;
+
+ uint32_t last_num_instances;
+ uint32_t last_first_instance;
+ uint32_t last_vertex_offset;
};
struct radv_cmd_pool {
uint32_t vgt_reuse_off;
};
+struct radv_binning_state {
+ uint32_t pa_sc_binner_cntl_0;
+ uint32_t db_dfsm_control;
+};
+
#define SI_GS_PER_ES 128
struct radv_pipeline {
struct radv_tessellation_state tess;
struct radv_gs_state gs;
struct radv_vs_state vs;
+ struct radv_binning_state bin;
uint32_t db_shader_control;
uint32_t shader_z_format;
unsigned prim;
uint32_t vtx_reuse_depth;
struct radv_prim_vertex_count prim_vertex_count;
bool can_use_guardband;
+ uint32_t pa_sc_cliprect_rule;
} graphics;
};
VkImageLayout layout,
unsigned queue_mask);
+bool radv_layout_dcc_compressed(const struct radv_image *image,
+ VkImageLayout layout,
+ unsigned queue_mask);
+
static inline bool
radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
{
uint32_t cb_dcc_control;
uint32_t cb_color_cmask_slice;
uint32_t cb_color_fmask_slice;
- uint32_t cb_clear_value0;
- uint32_t cb_clear_value1;
};
struct radv_ds_buffer_info {