radv: Implement VK_EXT_debug_report.

[mesa.git] / src / amd / vulkan / radv_private.h

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index b7c53d03fbdbfea70d89345a079696d9c28b8309..d51a669b383776529116a84f499ea0affb2cab2e 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -49,6 +49,7 @@
 #include "util/list.h"
 #include "main/macros.h"
 #include "vk_alloc.h"
+#include "vk_debug_report.h"
 
 #include "radv_radeon_winsys.h"
 #include "ac_binary.h"
@@ -81,6 +82,7 @@ typedef uint32_t xcb_window_t;
 #define MAX_RTS          8
 #define MAX_VIEWPORTS   16
 #define MAX_SCISSORS    16
+#define MAX_DISCARD_RECTANGLES 4
 #define MAX_PUSH_CONSTANTS_SIZE 128
 #define MAX_PUSH_DESCRIPTORS 32
 #define MAX_DYNAMIC_BUFFERS 16
@@ -295,6 +297,8 @@ struct radv_instance {
 
        uint64_t debug_flags;
        uint64_t perftest_flags;
+
+       struct vk_debug_report_instance             debug_report_callbacks;
 };
 
 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
@@ -739,7 +743,8 @@ enum radv_dynamic_state_bits {
        RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
        RADV_DYNAMIC_STENCIL_WRITE_MASK   = 1 << 7,
        RADV_DYNAMIC_STENCIL_REFERENCE    = 1 << 8,
-       RADV_DYNAMIC_ALL                  = (1 << 9) - 1,
+       RADV_DYNAMIC_DISCARD_RECTANGLE    = 1 << 9,
+       RADV_DYNAMIC_ALL                  = (1 << 10) - 1,
 };
 
 enum radv_cmd_dirty_bits {
@@ -754,11 +759,12 @@ enum radv_cmd_dirty_bits {
        RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK      = 1 << 6,
        RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK        = 1 << 7,
        RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE         = 1 << 8,
-       RADV_CMD_DIRTY_DYNAMIC_ALL                       = (1 << 9) - 1,
-       RADV_CMD_DIRTY_PIPELINE                          = 1 << 9,
-       RADV_CMD_DIRTY_INDEX_BUFFER                      = 1 << 10,
-       RADV_CMD_DIRTY_FRAMEBUFFER                       = 1 << 11,
-       RADV_CMD_DIRTY_VERTEX_BUFFER                     = 1 << 12,
+       RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE         = 1 << 9,
+       RADV_CMD_DIRTY_DYNAMIC_ALL                       = (1 << 10) - 1,
+       RADV_CMD_DIRTY_PIPELINE                          = 1 << 10,
+       RADV_CMD_DIRTY_INDEX_BUFFER                      = 1 << 11,
+       RADV_CMD_DIRTY_FRAMEBUFFER                       = 1 << 12,
+       RADV_CMD_DIRTY_VERTEX_BUFFER                     = 1 << 13,
 };
 
 enum radv_cmd_flush_bits {
@@ -803,6 +809,11 @@ struct radv_scissor_state {
        VkRect2D                                          scissors[MAX_SCISSORS];
 };
 
+struct radv_discard_rectangle_state {
+       uint32_t                                          count;
+       VkRect2D                                          rectangles[MAX_DISCARD_RECTANGLES];
+};
+
 struct radv_dynamic_state {
        /**
         * Bitmask of (1 << VK_DYNAMIC_STATE_*).
@@ -843,6 +854,8 @@ struct radv_dynamic_state {
                uint32_t                                  front;
                uint32_t                                  back;
        } stencil_reference;
+
+       struct radv_discard_rectangle_state               discard_rectangle;
 };
 
 extern const struct radv_dynamic_state default_dynamic_state;
@@ -903,6 +916,10 @@ struct radv_cmd_state {
        uint32_t                                      valid_descriptors;
        uint32_t                                      trace_id;
        uint32_t                                      last_ia_multi_vgt_param;
+
+       uint32_t last_num_instances;
+       uint32_t last_first_instance;
+       uint32_t last_vertex_offset;
 };
 
 struct radv_cmd_pool {
@@ -1239,6 +1256,7 @@ struct radv_pipeline {
                        uint32_t vtx_reuse_depth;
                        struct radv_prim_vertex_count prim_vertex_count;
                        bool can_use_guardband;
+                       uint32_t pa_sc_cliprect_rule;
                } graphics;
        };