#include "compiler/shader_enums.h"
#include "util/macros.h"
#include "util/list.h"
+#include "util/xmlconfig.h"
#include "main/macros.h"
#include "vk_alloc.h"
#include "vk_debug_report.h"
#define MAX_VIEWPORTS 16
#define MAX_SCISSORS 16
#define MAX_DISCARD_RECTANGLES 4
+#define MAX_SAMPLE_LOCATIONS 32
#define MAX_PUSH_CONSTANTS_SIZE 128
#define MAX_PUSH_DESCRIPTORS 32
#define MAX_DYNAMIC_UNIFORM_BUFFERS 16
#define NUM_META_FS_KEYS 12
#define RADV_MAX_DRM_DEVICES 8
#define MAX_VIEWS 8
+#define MAX_SO_STREAMS 4
+#define MAX_SO_BUFFERS 4
+#define MAX_SO_OUTPUTS 64
+#define MAX_INLINE_UNIFORM_BLOCK_SIZE (4ull * 1024 * 1024)
+#define MAX_INLINE_UNIFORM_BLOCK_COUNT 64
#define NUM_DEPTH_CLEAR_PIPELINES 3
uint32_t core_version,
const struct radv_instance_extension_table *instance,
const struct radv_device_extension_table *device);
+void *radv_lookup_physical_device_entrypoint_checked(const char *name,
+ uint32_t core_version,
+ const struct radv_instance_extension_table *instance);
struct radv_physical_device {
VK_LOADER_DATA _loader_data;
struct radeon_winsys *ws;
struct radeon_info rad_info;
- char path[20];
char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
uint8_t driver_uuid[VK_UUID_SIZE];
uint8_t device_uuid[VK_UUID_SIZE];
/* Whether DCC should be enabled for MSAA textures. */
bool dcc_msaa_allowed;
+ /* Whether LOAD_CONTEXT_REG packets are supported. */
+ bool has_load_ctx_reg_pkt;
+
+ /* Whether to enable the AMD_shader_ballot extension */
+ bool use_shader_ballot;
+
/* This is the drivers on-disk cache used as a fallback as opposed to
* the pipeline cache defined by apps.
*/
struct vk_debug_report_instance debug_report_callbacks;
struct radv_instance_extension_table enabled_extensions;
+
+ struct driOptionCache dri_options;
+ struct driOptionCache available_dri_options;
};
VkResult radv_init_wsi(struct radv_physical_device *physical_device);
struct radv_pipeline_key {
uint32_t instance_rate_inputs;
uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
+ uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
+ uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
+ uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
+ uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
uint64_t vertex_alpha_adjust;
+ uint32_t vertex_post_shuffle;
unsigned tess_input_vertices;
uint32_t col_format;
uint32_t is_int8;
radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
struct radv_pipeline_cache *cache,
const unsigned char *sha1,
- struct radv_shader_variant **variants);
+ struct radv_shader_variant **variants,
+ bool *found_in_application_cache);
void
radv_pipeline_cache_insert_shaders(struct radv_device *device,
VkPipelineLayout clear_color_p_layout;
VkPipelineLayout clear_depth_p_layout;
+
+ /* Optimized compute fast HTILE clear for stencil or depth only. */
+ VkPipeline clear_htile_mask_pipeline;
+ VkPipelineLayout clear_htile_mask_p_layout;
+ VkDescriptorSetLayout clear_htile_mask_ds_layout;
+
struct {
VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
VkPipelineLayout p_layout;
VkPipeline occlusion_query_pipeline;
VkPipeline pipeline_statistics_query_pipeline;
+ VkPipeline tfb_query_pipeline;
} query;
+
+ struct {
+ VkDescriptorSetLayout ds_layout;
+ VkPipelineLayout p_layout;
+ VkPipeline pipeline[MAX_SAMPLES_LOG2];
+ } fmask_expand;
};
/* queue types */
float sample_locations_2x[2][2];
float sample_locations_4x[4][2];
float sample_locations_8x[8][2];
- float sample_locations_16x[16][2];
- /* CIK and later */
+ /* GFX7 and later */
uint32_t gfx_init_size_dw;
struct radeon_winsys_bo *gfx_init;
uint32_t buffer_offset;
/* Only valid for combined image samplers and samplers */
- uint16_t has_sampler;
+ uint8_t has_sampler;
+ uint8_t sampler_offset;
/* In bytes */
size_t src_offset;
RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
- RADV_DYNAMIC_ALL = (1 << 10) - 1,
+ RADV_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
+ RADV_DYNAMIC_ALL = (1 << 11) - 1,
};
enum radv_cmd_dirty_bits {
RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
- RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
- RADV_CMD_DIRTY_PIPELINE = 1 << 10,
- RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
- RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
- RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
+ RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
+ RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 11) - 1,
+ RADV_CMD_DIRTY_PIPELINE = 1 << 11,
+ RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 12,
+ RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 13,
+ RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 14,
+ RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 15,
};
enum radv_cmd_flush_bits {
/* Pipeline query controls. */
RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
+ RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
VkDeviceSize offset;
};
+struct radv_streamout_binding {
+ struct radv_buffer *buffer;
+ VkDeviceSize offset;
+ VkDeviceSize size;
+};
+
+struct radv_streamout_state {
+ /* Mask of bound streamout buffers. */
+ uint8_t enabled_mask;
+
+ /* External state that comes from the last vertex stage, it must be
+ * set explicitely when binding a new graphics pipeline.
+ */
+ uint16_t stride_in_dw[MAX_SO_BUFFERS];
+ uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
+
+ /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
+ uint32_t hw_enabled_mask;
+
+ /* State of VGT_STRMOUT_(CONFIG|EN) */
+ bool streamout_enabled;
+};
+
struct radv_viewport_state {
uint32_t count;
VkViewport viewports[MAX_VIEWPORTS];
VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
};
+struct radv_sample_locations_state {
+ VkSampleCountFlagBits per_pixel;
+ VkExtent2D grid_size;
+ uint32_t count;
+ VkSampleLocationEXT locations[MAX_SAMPLE_LOCATIONS];
+};
+
struct radv_dynamic_state {
/**
* Bitmask of (1 << VK_DYNAMIC_STATE_*).
} stencil_reference;
struct radv_discard_rectangle_state discard_rectangle;
+
+ struct radv_sample_locations_state sample_location;
};
extern const struct radv_dynamic_state default_dynamic_state;
uint32_t cleared_views;
VkClearValue clear_value;
VkImageLayout current_layout;
+ struct radv_sample_locations_state sample_location;
};
struct radv_descriptor_state {
uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
};
+struct radv_subpass_sample_locs_state {
+ uint32_t subpass_idx;
+ struct radv_sample_locations_state sample_location;
+};
+
struct radv_cmd_state {
/* Vertex descriptors */
uint64_t vb_va;
const struct radv_subpass * subpass;
struct radv_dynamic_state dynamic;
struct radv_attachment_state * attachments;
+ struct radv_streamout_state streamout;
VkRect2D render_area;
+ uint32_t num_subpass_sample_locs;
+ struct radv_subpass_sample_locs_state * subpass_sample_locs;
+
/* Index buffer */
struct radv_buffer *index_buffer;
uint64_t index_offset;
/* Conditional rendering info. */
int predication_type; /* -1: disabled, 0: normal, 1: inverted */
uint64_t predication_va;
+
+ bool context_roll_without_scissor_emitted;
};
struct radv_cmd_pool {
struct radeon_cmdbuf *cs;
struct radv_cmd_state state;
struct radv_vertex_binding vertex_bindings[MAX_VBS];
+ struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
uint32_t queue_family_index;
uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
VkResult record_result;
- uint32_t gfx9_fence_offset;
- struct radeon_winsys_bo *gfx9_fence_bo;
+ uint64_t gfx9_fence_va;
uint32_t gfx9_fence_idx;
uint64_t gfx9_eop_bug_va;
* Whether a query pool has been resetted and we have to flush caches.
*/
bool pending_reset_query;
+
+ /**
+ * Bitmask of pending active query flushes.
+ */
+ enum radv_cmd_flush_bits active_query_flush_bits;
};
struct radv_image;
const VkViewport *viewports, bool can_use_guardband);
uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
bool instanced_draw, bool indirect_draw,
+ bool count_from_stream_output,
uint32_t draw_vertex_count);
void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
enum chip_class chip_class,
unsigned event, unsigned event_flags,
unsigned data_sel,
uint64_t va,
- uint32_t old_fence,
uint32_t new_fence,
uint64_t gfx9_eop_bug_va);
-void si_emit_wait_fence(struct radeon_cmdbuf *cs,
- uint64_t va, uint32_t ref,
- uint32_t mask);
+void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
+ uint32_t ref, uint32_t mask);
void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
enum chip_class chip_class,
uint32_t *fence_ptr, uint64_t va,
void **ptr);
void
radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
- const struct radv_subpass *subpass,
- bool transitions);
+ const struct radv_subpass *subpass);
bool
radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
unsigned size, unsigned alignmnet,
void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
-void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples);
-unsigned radv_cayman_get_maxdist(int log_samples);
+void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
+unsigned radv_get_default_max_sample_dist(int log_samples);
void radv_device_init_msaa(struct radv_device *device);
void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
int cb_idx,
uint32_t color_values[2]);
-void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image,
- bool value);
+void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_image *image, bool value);
+
+void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_image *image, bool value);
+
uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
struct radeon_winsys_bo *bo,
uint64_t offset, uint64_t size, uint32_t value);
struct radeon_cmdbuf *cs,
uint32_t sh_offset, uint64_t va, bool global)
{
- bool use_32bit_pointers = HAVE_32BIT_POINTERS && !global;
+ bool use_32bit_pointers = !global;
radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
};
struct radv_vertex_elements_info {
- uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
uint32_t format_size[MAX_VERTEX_ATTRIBS];
- uint32_t binding[MAX_VERTEX_ATTRIBS];
- uint32_t offset[MAX_VERTEX_ATTRIBS];
- uint32_t count;
};
struct radv_ia_multi_vgt_param_helpers {
VkShaderStageFlags active_stages;
struct radeon_cmdbuf cs;
+ uint32_t ctx_cs_hash;
+ struct radeon_cmdbuf ctx_cs;
struct radv_vertex_elements_info vertex_elements;
uint32_t binding_stride[MAX_VBS];
+ uint8_t num_vertex_bindings;
uint32_t user_data_0[MESA_SHADER_STAGES];
union {
unsigned max_waves;
unsigned scratch_bytes_per_wave;
+
+ /* Not NULL if graphics pipeline uses streamout. */
+ struct radv_shader_variant *streamout_shader;
};
static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
bool radv_dcc_formats_compatible(VkFormat format1,
VkFormat format2);
+bool radv_device_supports_etc(struct radv_physical_device *physical_device);
struct radv_fmask_info {
uint64_t offset;
unsigned slice_tile_max;
};
+
+struct radv_image_plane {
+ VkFormat format;
+ struct radeon_surf surface;
+ uint64_t offset;
+};
+
struct radv_image {
VkImageType type;
/* The original VkFormat provided by the client. This may not match any
uint64_t dcc_offset;
uint64_t htile_offset;
bool tc_compatible_htile;
- struct radeon_surf surface;
struct radv_fmask_info fmask;
struct radv_cmask_info cmask;
uint64_t clear_value_offset;
+ uint64_t fce_pred_offset;
uint64_t dcc_pred_offset;
+ /*
+ * Metadata for the TC-compat zrange workaround. If the 32-bit value
+ * stored at this offset is UINT_MAX, the driver will emit
+ * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
+ * SET_CONTEXT_REG packet.
+ */
+ uint64_t tc_compat_zrange_offset;
+
/* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
VkDeviceMemory owned_memory;
+
+ unsigned plane_count;
+ struct radv_image_plane planes[0];
};
/* Whether the image has a htile that is known consistent with the contents of
static inline bool
radv_image_has_dcc(const struct radv_image *image)
{
- return image->surface.dcc_size;
+ return image->planes[0].surface.dcc_size;
}
/**
radv_dcc_enabled(const struct radv_image *image, unsigned level)
{
return radv_image_has_dcc(image) &&
- level < image->surface.num_dcc_levels;
+ level < image->planes[0].surface.num_dcc_levels;
}
/**
static inline bool
radv_image_has_htile(const struct radv_image *image)
{
- return image->surface.htile_size;
+ return image->planes[0].surface.htile_size;
}
/**
struct radv_image *image,
struct radeon_bo_metadata *metadata);
+void
+radv_image_override_offset_stride(struct radv_device *device,
+ struct radv_image *image,
+ uint64_t offset, uint32_t stride);
+
+union radv_descriptor {
+ struct {
+ uint32_t plane0_descriptor[8];
+ uint32_t fmask_descriptor[8];
+ };
+ struct {
+ uint32_t plane_descriptors[3][8];
+ };
+};
+
struct radv_image_view {
struct radv_image *image; /**< VkImageViewCreateInfo::image */
struct radeon_winsys_bo *bo;
VkImageViewType type;
VkImageAspectFlags aspect_mask;
VkFormat vk_format;
+ unsigned plane_id;
+ bool multiple_planes;
uint32_t base_layer;
uint32_t layer_count;
uint32_t base_mip;
uint32_t level_count;
VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
- uint32_t descriptor[16];
+ union radv_descriptor descriptor;
/* Descriptor for use as a storage image as opposed to a sampled image.
* This has a few differences for cube maps (e.g. type).
*/
- uint32_t storage_descriptor[16];
+ union radv_descriptor storage_descriptor;
};
struct radv_image_create_info {
const VkImageCreateInfo *vk_info;
bool scanout;
bool no_metadata_planes;
+ const struct radeon_bo_metadata *bo_metadata;
};
VkResult radv_image_create(VkDevice _device,
struct radv_device *device,
const VkImageViewCreateInfo* pCreateInfo);
+VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask);
+
+struct radv_sampler_ycbcr_conversion {
+ VkFormat format;
+ VkSamplerYcbcrModelConversion ycbcr_model;
+ VkSamplerYcbcrRange ycbcr_range;
+ VkComponentMapping components;
+ VkChromaLocation chroma_offsets[2];
+ VkFilter chroma_filter;
+};
+
struct radv_buffer_view {
struct radeon_winsys_bo *bo;
VkFormat vk_format;
struct radv_sampler {
uint32_t state[4];
+ struct radv_sampler_ycbcr_conversion *ycbcr_sampler;
};
struct radv_color_buffer_info {
uint64_t cb_color_cmask;
uint64_t cb_color_fmask;
uint64_t cb_dcc_base;
- uint32_t cb_color_pitch;
uint32_t cb_color_slice;
uint32_t cb_color_view;
uint32_t cb_color_info;
uint32_t cb_dcc_control;
uint32_t cb_color_cmask_slice;
uint32_t cb_color_fmask_slice;
+ union {
+ uint32_t cb_color_pitch; // GFX6-GFX8
+ uint32_t cb_mrt_epitch; // GFX9+
+ };
};
struct radv_ds_buffer_info {
};
struct radv_subpass {
+ uint32_t attachment_count;
+ struct radv_subpass_attachment * attachments;
+
uint32_t input_count;
uint32_t color_count;
struct radv_subpass_attachment * input_attachments;
struct radv_subpass_attachment * color_attachments;
struct radv_subpass_attachment * resolve_attachments;
- struct radv_subpass_attachment depth_stencil_attachment;
+ struct radv_subpass_attachment * depth_stencil_attachment;
/** Subpass has at least one resolve attachment */
bool has_resolve;
+ /** Subpass has at least one color attachment */
+ bool has_color_att;
+
struct radv_subpass_barrier start_barrier;
uint32_t view_mask;
VkAttachmentLoadOp stencil_load_op;
VkImageLayout initial_layout;
VkImageLayout final_layout;
- uint32_t view_mask;
+
+ /* The subpass id in which the attachment will be used first/last. */
+ uint32_t first_subpass_idx;
+ uint32_t last_subpass_idx;
};
struct radv_render_pass {
radv_update_descriptor_set_with_template(struct radv_device *device,
struct radv_cmd_buffer *cmd_buffer,
struct radv_descriptor_set *set,
- VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
+ VkDescriptorUpdateTemplate descriptorUpdateTemplate,
const void *pData);
void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image, uint32_t value);
+void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_image *image);
+
struct radv_fence {
struct radeon_winsys_fence *fence;
struct wsi_fence *fence_wsi;
- bool submitted;
- bool signalled;
uint32_t syncobj;
uint32_t temp_syncobj;
int nir_count,
const struct radv_nir_compiler_options *options);
+unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
+ const struct nir_shader *nir);
+
/* radv_shader_info.h */
struct radv_shader_info;
const struct radv_nir_compiler_options *options,
struct radv_shader_info *info);
+void radv_nir_shader_info_init(struct radv_shader_info *info);
+
struct radeon_winsys_sem;
+uint64_t radv_get_current_time(void);
+
#define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
\
static inline struct __radv_type * \
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
-RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
+RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplate)
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
+RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion, VkSamplerYcbcrConversion)
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
projects / mesa.git / blobdiff