#define NUM_META_FS_KEYS 12
#define RADV_MAX_DRM_DEVICES 8
#define MAX_VIEWS 8
+#define MAX_SO_STREAMS 4
+#define MAX_SO_BUFFERS 4
+#define MAX_SO_OUTPUTS 64
#define NUM_DEPTH_CLEAR_PIPELINES 3
*/
#define RADV_BUFFER_OPS_CS_THRESHOLD 4096
+#define RADV_BUFFER_UPDATE_THRESHOLD 1024
+
enum radv_mem_heap {
RADV_MEM_HEAP_VRAM,
RADV_MEM_HEAP_VRAM_CPU_ACCESS,
VkPhysicalDeviceMemoryProperties memory_properties;
enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
+ drmPciBusInfo bus_info;
+
struct radv_device_extension_table supported_extensions;
};
VkPipelineLayout clear_color_p_layout;
VkPipelineLayout clear_depth_p_layout;
+
+ /* Optimized compute fast HTILE clear for stencil or depth only. */
+ VkPipeline clear_htile_mask_pipeline;
+ VkPipelineLayout clear_htile_mask_p_layout;
+ VkDescriptorSetLayout clear_htile_mask_ds_layout;
+
struct {
VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
VkPipeline pipeline;
VkPipeline pipeline_3d;
} btoi;
+ struct {
+ VkPipelineLayout img_p_layout;
+ VkDescriptorSetLayout img_ds_layout;
+ VkPipeline pipeline;
+ } btoi_r32g32b32;
struct {
VkPipelineLayout img_p_layout;
VkDescriptorSetLayout img_ds_layout;
VkPipeline pipeline;
VkPipeline pipeline_3d;
} itoi;
+ struct {
+ VkPipelineLayout img_p_layout;
+ VkDescriptorSetLayout img_ds_layout;
+ VkPipeline pipeline;
+ } itoi_r32g32b32;
struct {
VkPipelineLayout img_p_layout;
VkDescriptorSetLayout img_ds_layout;
VkPipeline pipeline;
VkPipeline pipeline_3d;
} cleari;
+ struct {
+ VkPipelineLayout img_p_layout;
+ VkDescriptorSetLayout img_ds_layout;
+ VkPipeline pipeline;
+ } cleari_r32g32b32;
struct {
VkPipelineLayout p_layout;
VkPipelineLayout p_layout;
VkPipeline occlusion_query_pipeline;
VkPipeline pipeline_statistics_query_pipeline;
+ VkPipeline tfb_query_pipeline;
} query;
};
RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
+ RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 14,
};
enum radv_cmd_flush_bits {
/* Pipeline query controls. */
RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
+ RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
VkDeviceSize offset;
};
+struct radv_streamout_binding {
+ struct radv_buffer *buffer;
+ VkDeviceSize offset;
+ VkDeviceSize size;
+};
+
+struct radv_streamout_state {
+ /* Mask of bound streamout buffers. */
+ uint8_t enabled_mask;
+
+ /* External state that comes from the last vertex stage, it must be
+ * set explicitely when binding a new graphics pipeline.
+ */
+ uint16_t stride_in_dw[MAX_SO_BUFFERS];
+ uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
+
+ /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
+ uint32_t hw_enabled_mask;
+
+ /* State of VGT_STRMOUT_(CONFIG|EN) */
+ bool streamout_enabled;
+};
+
struct radv_viewport_state {
uint32_t count;
VkViewport viewports[MAX_VIEWPORTS];
const struct radv_subpass * subpass;
struct radv_dynamic_state dynamic;
struct radv_attachment_state * attachments;
+ struct radv_streamout_state streamout;
VkRect2D render_area;
/* Index buffer */
struct radeon_cmdbuf *cs;
struct radv_cmd_state state;
struct radv_vertex_binding vertex_bindings[MAX_VBS];
+ struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
uint32_t queue_family_index;
uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
uint32_t new_fence,
uint64_t gfx9_eop_bug_va);
-void si_emit_wait_fence(struct radeon_cmdbuf *cs,
- uint64_t va, uint32_t ref,
- uint32_t mask);
+void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
+ uint32_t ref, uint32_t mask);
void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
enum chip_class chip_class,
uint32_t *fence_ptr, uint64_t va,
int cb_idx,
uint32_t color_values[2]);
-void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image,
- bool value);
+void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_image *image, bool value);
+
uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
struct radeon_winsys_bo *bo,
uint64_t offset, uint64_t size, uint32_t value);
struct radeon_cmdbuf *cs,
uint32_t sh_offset, uint64_t va, bool global)
{
- bool use_32bit_pointers = HAVE_32BIT_POINTERS && !global;
+ bool use_32bit_pointers = !global;
radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
unsigned max_waves;
unsigned scratch_bytes_per_wave;
+
+ /* Not NULL if graphics pipeline uses streamout. */
+ struct radv_shader_variant *streamout_shader;
};
static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
struct radv_fmask_info fmask;
struct radv_cmask_info cmask;
uint64_t clear_value_offset;
- uint64_t dcc_pred_offset;
+ uint64_t fce_pred_offset;
+
+ /*
+ * Metadata for the TC-compat zrange workaround. If the 32-bit value
+ * stored at this offset is UINT_MAX, the driver will emit
+ * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
+ * SET_CONTEXT_REG packet.
+ */
+ uint64_t tc_compat_zrange_offset;
/* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
VkDeviceMemory owned_memory;
projects / mesa.git / blobdiff