ac: add has_load_ctx_reg_pkt to ac_gpu_info

[mesa.git] / src / amd / vulkan / radv_private.h

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 9bcb2baf97e5868b75064efe11c682242d4ce2ba..f252270b207d59d6bbd9047cd75dfd001a7fe662 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -280,9 +280,7 @@ struct radv_physical_device {
        int master_fd;
        struct wsi_device                       wsi_device;
 
-       bool has_rbplus; /* if RB+ register exist */
        bool rbplus_allowed; /* if RB+ is allowed */
-       bool has_clear_state;
        bool cpdma_prefetch_writes_memory;
        bool has_scissor_bug;
        bool has_tc_compat_zrange_bug;
@@ -293,15 +291,9 @@ struct radv_physical_device {
        /* Whether DCC should be enabled for MSAA textures. */
        bool dcc_msaa_allowed;
 
-       /* Whether LOAD_CONTEXT_REG packets are supported. */
-       bool has_load_ctx_reg_pkt;
-
        /* Whether to enable the AMD_shader_ballot extension */
        bool use_shader_ballot;
 
-       /* Whether DISABLE_CONSTANT_ENCODE_REG is supported. */
-       bool has_dcc_constant_encode;
-
        /* Number of threads per wave. */
        uint8_t ps_wave_size;
        uint8_t cs_wave_size;
@@ -705,7 +697,6 @@ struct radv_device {
        struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
 
        bool always_use_syncobj;
-       bool has_distributed_tess;
        bool pbb_allowed;
        bool dfsm_allowed;
        uint32_t tess_offchip_block_dw_size;