* propagating errors. Might be useful to plug in a stack trace here.
*/
+struct radv_image_view;
struct radv_instance;
VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
int master_fd;
struct wsi_device wsi_device;
- bool has_rbplus; /* if RB+ register exist */
bool rbplus_allowed; /* if RB+ is allowed */
- bool has_clear_state;
bool cpdma_prefetch_writes_memory;
bool has_scissor_bug;
bool has_tc_compat_zrange_bug;
/* Whether DCC should be enabled for MSAA textures. */
bool dcc_msaa_allowed;
- /* Whether LOAD_CONTEXT_REG packets are supported. */
- bool has_load_ctx_reg_pkt;
-
/* Whether to enable the AMD_shader_ballot extension */
bool use_shader_ballot;
- /* Whether DISABLE_CONSTANT_ENCODE_REG is supported. */
- bool has_dcc_constant_encode;
-
/* Number of threads per wave. */
uint8_t ps_wave_size;
uint8_t cs_wave_size;
struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
bool always_use_syncobj;
- bool has_distributed_tess;
bool pbb_allowed;
bool dfsm_allowed;
uint32_t tess_offchip_block_dw_size;
const char *
radv_get_perftest_option_name(int id);
+struct radv_color_buffer_info {
+ uint64_t cb_color_base;
+ uint64_t cb_color_cmask;
+ uint64_t cb_color_fmask;
+ uint64_t cb_dcc_base;
+ uint32_t cb_color_slice;
+ uint32_t cb_color_view;
+ uint32_t cb_color_info;
+ uint32_t cb_color_attrib;
+ uint32_t cb_color_attrib2; /* GFX9 and later */
+ uint32_t cb_color_attrib3; /* GFX10 and later */
+ uint32_t cb_dcc_control;
+ uint32_t cb_color_cmask_slice;
+ uint32_t cb_color_fmask_slice;
+ union {
+ uint32_t cb_color_pitch; // GFX6-GFX8
+ uint32_t cb_mrt_epitch; // GFX9+
+ };
+};
+
+struct radv_ds_buffer_info {
+ uint64_t db_z_read_base;
+ uint64_t db_stencil_read_base;
+ uint64_t db_z_write_base;
+ uint64_t db_stencil_write_base;
+ uint64_t db_htile_data_base;
+ uint32_t db_depth_info;
+ uint32_t db_z_info;
+ uint32_t db_stencil_info;
+ uint32_t db_depth_view;
+ uint32_t db_depth_size;
+ uint32_t db_depth_slice;
+ uint32_t db_htile_surface;
+ uint32_t pa_su_poly_offset_db_fmt_cntl;
+ uint32_t db_z_info2; /* GFX9 only */
+ uint32_t db_stencil_info2; /* GFX9 only */
+ float offset_scale;
+};
+
+void
+radv_initialise_color_surface(struct radv_device *device,
+ struct radv_color_buffer_info *cb,
+ struct radv_image_view *iview);
+void
+radv_initialise_ds_surface(struct radv_device *device,
+ struct radv_ds_buffer_info *ds,
+ struct radv_image_view *iview);
+
/**
* Attachment state when recording a renderpass instance.
*
uint32_t cleared_views;
VkClearValue clear_value;
VkImageLayout current_layout;
+ bool current_in_render_loop;
struct radv_sample_locations_state sample_location;
+
+ union {
+ struct radv_color_buffer_info cb;
+ struct radv_ds_buffer_info ds;
+ };
+ struct radv_image_view *iview;
};
struct radv_descriptor_state {
void radv_device_init_msaa(struct radv_device *device);
void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image,
+ const struct radv_image_view *iview,
VkClearDepthStencilValue ds_clear_value,
VkImageAspectFlags aspects);
#define RADV_HASH_SHADER_SISCHED (1 << 1)
#define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
#define RADV_HASH_SHADER_NO_NGG (1 << 3)
+#define RADV_HASH_SHADER_CS_WAVE32 (1 << 4)
+#define RADV_HASH_SHADER_PS_WAVE32 (1 << 5)
+#define RADV_HASH_SHADER_GE_WAVE32 (1 << 6)
void
radv_hash_shaders(unsigned char *hash,
* the image. */
bool radv_layout_has_htile(const struct radv_image *image,
VkImageLayout layout,
+ bool in_render_loop,
unsigned queue_mask);
/* Whether the image has a htile that is known consistent with the contents of
*/
bool radv_layout_is_htile_compressed(const struct radv_image *image,
VkImageLayout layout,
+ bool in_render_loop,
unsigned queue_mask);
bool radv_layout_can_fast_clear(const struct radv_image *image,
VkImageLayout layout,
+ bool in_render_loop,
unsigned queue_mask);
-bool radv_layout_dcc_compressed(const struct radv_image *image,
+bool radv_layout_dcc_compressed(const struct radv_device *device,
+ const struct radv_image *image,
VkImageLayout layout,
+ bool in_render_loop,
unsigned queue_mask);
/**
return va;
}
+static inline uint64_t
+radv_get_tc_compat_zrange_va(const struct radv_image *image,
+ uint32_t base_level)
+{
+ uint64_t va = radv_buffer_get_va(image->bo);
+ va += image->offset + image->tc_compat_zrange_offset + base_level * 4;
+ return va;
+}
+
+static inline uint64_t
+radv_get_ds_clear_value_va(const struct radv_image *image,
+ uint32_t base_level)
+{
+ uint64_t va = radv_buffer_get_va(image->bo);
+ va += image->offset + image->clear_value_offset + base_level * 8;
+ return va;
+}
+
unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
static inline uint32_t
const VkAllocationCallbacks *alloc,
VkImage *out_image_h);
+struct radv_image_view_extra_create_info {
+ bool disable_compression;
+};
+
void radv_image_view_init(struct radv_image_view *view,
struct radv_device *device,
- const VkImageViewCreateInfo* pCreateInfo);
+ const VkImageViewCreateInfo *pCreateInfo,
+ const struct radv_image_view_extra_create_info* extra_create_info);
VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask);
struct radv_sampler_ycbcr_conversion *ycbcr_sampler;
};
-struct radv_color_buffer_info {
- uint64_t cb_color_base;
- uint64_t cb_color_cmask;
- uint64_t cb_color_fmask;
- uint64_t cb_dcc_base;
- uint32_t cb_color_slice;
- uint32_t cb_color_view;
- uint32_t cb_color_info;
- uint32_t cb_color_attrib;
- uint32_t cb_color_attrib2; /* GFX9 and later */
- uint32_t cb_color_attrib3; /* GFX10 and later */
- uint32_t cb_dcc_control;
- uint32_t cb_color_cmask_slice;
- uint32_t cb_color_fmask_slice;
- union {
- uint32_t cb_color_pitch; // GFX6-GFX8
- uint32_t cb_mrt_epitch; // GFX9+
- };
-};
-
-struct radv_ds_buffer_info {
- uint64_t db_z_read_base;
- uint64_t db_stencil_read_base;
- uint64_t db_z_write_base;
- uint64_t db_stencil_write_base;
- uint64_t db_htile_data_base;
- uint32_t db_depth_info;
- uint32_t db_z_info;
- uint32_t db_stencil_info;
- uint32_t db_depth_view;
- uint32_t db_depth_size;
- uint32_t db_depth_slice;
- uint32_t db_htile_surface;
- uint32_t pa_su_poly_offset_db_fmt_cntl;
- uint32_t db_z_info2; /* GFX9 only */
- uint32_t db_stencil_info2; /* GFX9 only */
- float offset_scale;
-};
-
-struct radv_attachment_info {
- union {
- struct radv_color_buffer_info cb;
- struct radv_ds_buffer_info ds;
- };
- struct radv_image_view *attachment;
-};
-
struct radv_framebuffer {
uint32_t width;
uint32_t height;
uint32_t layers;
uint32_t attachment_count;
- struct radv_attachment_info attachments[0];
+ struct radv_image_view *attachments[0];
};
struct radv_subpass_barrier {
struct radv_subpass_attachment {
uint32_t attachment;
VkImageLayout layout;
+ bool in_render_loop;
};
struct radv_subpass {
projects / mesa.git / blobdiff