ac: add has_load_ctx_reg_pkt to ac_gpu_info

[mesa.git] / src / amd / vulkan / radv_private.h

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index a6af335111478949c76dec0d1efefc03d77f897b..f252270b207d59d6bbd9047cd75dfd001a7fe662 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -280,9 +280,7 @@ struct radv_physical_device {
        int master_fd;
        struct wsi_device                       wsi_device;
 
-       bool has_rbplus; /* if RB+ register exist */
        bool rbplus_allowed; /* if RB+ is allowed */
-       bool has_clear_state;
        bool cpdma_prefetch_writes_memory;
        bool has_scissor_bug;
        bool has_tc_compat_zrange_bug;
@@ -293,15 +291,9 @@ struct radv_physical_device {
        /* Whether DCC should be enabled for MSAA textures. */
        bool dcc_msaa_allowed;
 
-       /* Whether LOAD_CONTEXT_REG packets are supported. */
-       bool has_load_ctx_reg_pkt;
-
        /* Whether to enable the AMD_shader_ballot extension */
        bool use_shader_ballot;
 
-       /* Whether DISABLE_CONSTANT_ENCODE_REG is supported. */
-       bool has_dcc_constant_encode;
-
        /* Number of threads per wave. */
        uint8_t ps_wave_size;
        uint8_t cs_wave_size;
@@ -705,7 +697,6 @@ struct radv_device {
        struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
 
        bool always_use_syncobj;
-       bool has_distributed_tess;
        bool pbb_allowed;
        bool dfsm_allowed;
        uint32_t tess_offchip_block_dw_size;
@@ -1098,12 +1089,14 @@ struct radv_attachment_state {
        uint32_t                                     cleared_views;
        VkClearValue                                 clear_value;
        VkImageLayout                                current_layout;
+       bool                                         current_in_render_loop;
        struct radv_sample_locations_state           sample_location;
 
        union {
                struct radv_color_buffer_info cb;
                struct radv_ds_buffer_info ds;
        };
+       struct radv_image_view *iview;
 };
 
 struct radv_descriptor_state {
@@ -1329,7 +1322,7 @@ unsigned radv_get_default_max_sample_dist(int log_samples);
 void radv_device_init_msaa(struct radv_device *device);
 
 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
-                                  struct radv_image *image,
+                                  const struct radv_image_view *iview,
                                   VkClearDepthStencilValue ds_clear_value,
                                   VkImageAspectFlags aspects);
 
@@ -1421,6 +1414,9 @@ struct radv_shader_module;
 #define RADV_HASH_SHADER_SISCHED             (1 << 1)
 #define RADV_HASH_SHADER_UNSAFE_MATH         (1 << 2)
 #define RADV_HASH_SHADER_NO_NGG              (1 << 3)
+#define RADV_HASH_SHADER_CS_WAVE32           (1 << 4)
+#define RADV_HASH_SHADER_PS_WAVE32           (1 << 5)
+#define RADV_HASH_SHADER_GE_WAVE32           (1 << 6)
 
 void
 radv_hash_shaders(unsigned char *hash,
@@ -1664,6 +1660,7 @@ struct radv_image {
  * the image. */
 bool radv_layout_has_htile(const struct radv_image *image,
                            VkImageLayout layout,
+                           bool in_render_loop,
                            unsigned queue_mask);
 
 /* Whether the image has a htile  that is known consistent with the contents of
@@ -1674,14 +1671,18 @@ bool radv_layout_has_htile(const struct radv_image *image,
  */
 bool radv_layout_is_htile_compressed(const struct radv_image *image,
                                      VkImageLayout layout,
+                                     bool in_render_loop,
                                      unsigned queue_mask);
 
 bool radv_layout_can_fast_clear(const struct radv_image *image,
                                VkImageLayout layout,
+                               bool in_render_loop,
                                unsigned queue_mask);
 
-bool radv_layout_dcc_compressed(const struct radv_image *image,
+bool radv_layout_dcc_compressed(const struct radv_device *device,
+                               const struct radv_image *image,
                                VkImageLayout layout,
+                               bool in_render_loop,
                                unsigned queue_mask);
 
 /**
@@ -1795,6 +1796,24 @@ radv_image_get_dcc_pred_va(const struct radv_image *image,
        return va;
 }
 
+static inline uint64_t
+radv_get_tc_compat_zrange_va(const struct radv_image *image,
+                            uint32_t base_level)
+{
+       uint64_t va = radv_buffer_get_va(image->bo);
+       va += image->offset + image->tc_compat_zrange_offset + base_level * 4;
+       return va;
+}
+
+static inline uint64_t
+radv_get_ds_clear_value_va(const struct radv_image *image,
+                          uint32_t base_level)
+{
+       uint64_t va = radv_buffer_get_va(image->bo);
+       va += image->offset + image->clear_value_offset + base_level * 8;
+       return va;
+}
+
 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
 
 static inline uint32_t
@@ -1876,9 +1895,14 @@ radv_image_from_gralloc(VkDevice device_h,
                        const VkAllocationCallbacks *alloc,
                        VkImage *out_image_h);
 
+struct radv_image_view_extra_create_info {
+       bool disable_compression;
+};
+
 void radv_image_view_init(struct radv_image_view *view,
                          struct radv_device *device,
-                         const VkImageViewCreateInfo* pCreateInfo);
+                         const VkImageViewCreateInfo *pCreateInfo,
+                         const struct radv_image_view_extra_create_info* extra_create_info);
 
 VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask);
 
@@ -1970,6 +1994,7 @@ void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
 struct radv_subpass_attachment {
        uint32_t         attachment;
        VkImageLayout    layout;
+       bool             in_render_loop;
 };
 
 struct radv_subpass {