#include "ac_llvm_util.h"
#include "radv_descriptor_set.h"
#include "radv_extensions.h"
-#include "radv_cs.h"
+#include "sid.h"
#include <llvm-c/TargetMachine.h>
#include "wsi_common.h"
#include "wsi_common_display.h"
+struct gfx10_format {
+ unsigned img_format:9;
+
+ /* Various formats are only supported with workarounds for vertex fetch,
+ * and some 32_32_32 formats are supported natively, but only for buffers
+ * (possibly with some image support, actually, but no filtering). */
+ bool buffers_only:1;
+};
+
+#include "gfx10_format_table.h"
+
#define ATI_VENDOR_ID 0x1002
#define MAX_VBS 32
#define MAX_VIEWPORTS 16
#define MAX_SCISSORS 16
#define MAX_DISCARD_RECTANGLES 4
+#define MAX_SAMPLE_LOCATIONS 32
#define MAX_PUSH_CONSTANTS_SIZE 128
#define MAX_PUSH_DESCRIPTORS 32
#define MAX_DYNAMIC_UNIFORM_BUFFERS 16
uint32_t core_version,
const struct radv_instance_extension_table *instance,
const struct radv_device_extension_table *device);
+void *radv_lookup_physical_device_entrypoint_checked(const char *name,
+ uint32_t core_version,
+ const struct radv_instance_extension_table *instance);
struct radv_physical_device {
VK_LOADER_DATA _loader_data;
/* Whether LOAD_CONTEXT_REG packets are supported. */
bool has_load_ctx_reg_pkt;
+ /* Whether to enable the AMD_shader_ballot extension */
+ bool use_shader_ballot;
+
+ /* Whether DISABLE_CONSTANT_ENCODE_REG is supported. */
+ bool has_dcc_constant_encode;
+
/* This is the drivers on-disk cache used as a fallback as opposed to
* the pipeline cache defined by apps.
*/
uint32_t optimisations_disabled : 1;
};
+struct radv_shader_binary;
+struct radv_shader_variant;
+
void
radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
struct radv_device *device);
radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
const void *data, size_t size);
-struct radv_shader_variant;
-
bool
radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
struct radv_pipeline_cache *cache,
struct radv_pipeline_cache *cache,
const unsigned char *sha1,
struct radv_shader_variant **variants,
- const void *const *codes,
- const unsigned *code_sizes);
+ struct radv_shader_binary *const *binaries);
enum radv_blit_ds_layout {
RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
VkPipeline i_pipeline;
VkPipeline srgb_pipeline;
} rc[MAX_SAMPLES_LOG2];
+
+ VkPipeline depth_zero_pipeline;
+ struct {
+ VkPipeline average_pipeline;
+ VkPipeline max_pipeline;
+ VkPipeline min_pipeline;
+ } depth[MAX_SAMPLES_LOG2];
+
+ VkPipeline stencil_zero_pipeline;
+ struct {
+ VkPipeline max_pipeline;
+ VkPipeline min_pipeline;
+ } stencil[MAX_SAMPLES_LOG2];
} resolve_compute;
struct {
VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
VkPipeline pipeline[NUM_META_FS_KEYS];
} rc[MAX_SAMPLES_LOG2];
+
+ VkRenderPass depth_render_pass;
+ VkPipeline depth_zero_pipeline;
+ struct {
+ VkPipeline average_pipeline;
+ VkPipeline max_pipeline;
+ VkPipeline min_pipeline;
+ } depth[MAX_SAMPLES_LOG2];
+
+ VkRenderPass stencil_render_pass;
+ VkPipeline stencil_zero_pipeline;
+ struct {
+ VkPipeline max_pipeline;
+ VkPipeline min_pipeline;
+ } stencil[MAX_SAMPLES_LOG2];
} resolve_fragment;
struct {
float sample_locations_2x[2][2];
float sample_locations_4x[4][2];
float sample_locations_8x[8][2];
- float sample_locations_16x[16][2];
- /* CIK and later */
+ /* GFX7 and later */
uint32_t gfx_init_size_dw;
struct radeon_winsys_bo *gfx_init;
RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
- RADV_DYNAMIC_ALL = (1 << 10) - 1,
+ RADV_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
+ RADV_DYNAMIC_ALL = (1 << 11) - 1,
};
enum radv_cmd_dirty_bits {
RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
- RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
- RADV_CMD_DIRTY_PIPELINE = 1 << 10,
- RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
- RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
- RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
- RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 14,
+ RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
+ RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 11) - 1,
+ RADV_CMD_DIRTY_PIPELINE = 1 << 11,
+ RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 12,
+ RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 13,
+ RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 14,
+ RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 15,
};
enum radv_cmd_flush_bits {
- RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
- /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
- RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
- /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
- RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
- /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
- RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
- /* Same as above, but only writes back and doesn't invalidate */
- RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
+ /* Instruction cache. */
+ RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
+ /* Scalar L1 cache. */
+ RADV_CMD_FLAG_INV_SCACHE = 1 << 1,
+ /* Vector L1 cache. */
+ RADV_CMD_FLAG_INV_VCACHE = 1 << 2,
+ /* L2 cache + L2 metadata cache writeback & invalidate.
+ * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
+ RADV_CMD_FLAG_INV_L2 = 1 << 3,
+ /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
+ * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
+ * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
+ RADV_CMD_FLAG_WB_L2 = 1 << 4,
/* Framebuffer caches */
- RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
- RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
- RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
- RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
+ RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
+ RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
+ RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
+ RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
/* Engine synchronization. */
- RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
- RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
- RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
- RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
+ RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
+ RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
+ RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
+ RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
/* Pipeline query controls. */
- RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
- RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
- RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
+ RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
+ RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
+ RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
};
+struct radv_sample_locations_state {
+ VkSampleCountFlagBits per_pixel;
+ VkExtent2D grid_size;
+ uint32_t count;
+ VkSampleLocationEXT locations[MAX_SAMPLE_LOCATIONS];
+};
+
struct radv_dynamic_state {
/**
* Bitmask of (1 << VK_DYNAMIC_STATE_*).
} stencil_reference;
struct radv_discard_rectangle_state discard_rectangle;
+
+ struct radv_sample_locations_state sample_location;
};
extern const struct radv_dynamic_state default_dynamic_state;
uint32_t cleared_views;
VkClearValue clear_value;
VkImageLayout current_layout;
+ struct radv_sample_locations_state sample_location;
};
struct radv_descriptor_state {
uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
};
+struct radv_subpass_sample_locs_state {
+ uint32_t subpass_idx;
+ struct radv_sample_locations_state sample_location;
+};
+
struct radv_cmd_state {
/* Vertex descriptors */
uint64_t vb_va;
struct radv_streamout_state streamout;
VkRect2D render_area;
+ uint32_t num_subpass_sample_locs;
+ struct radv_subpass_sample_locs_state * subpass_sample_locs;
+
/* Index buffer */
struct radv_buffer *index_buffer;
uint64_t index_offset;
* Whether a query pool has been resetted and we have to flush caches.
*/
bool pending_reset_query;
+
+ /**
+ * Bitmask of pending active query flushes.
+ */
+ enum radv_cmd_flush_bits active_query_flush_bits;
};
struct radv_image;
+struct radv_image_view;
bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
+void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
+ VkImageAspectFlags aspects,
+ VkResolveModeFlagBitsKHR resolve_mode);
void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
-void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples);
-unsigned radv_cayman_get_maxdist(int log_samples);
+void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
+ VkImageAspectFlags aspects,
+ VkResolveModeFlagBitsKHR resolve_mode);
+void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
+unsigned radv_get_default_max_sample_dist(int log_samples);
void radv_device_init_msaa(struct radv_device *device);
void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
VkImageAspectFlags aspects);
void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image,
+ const struct radv_image_view *iview,
int cb_idx,
uint32_t color_values[2]);
void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image, bool value);
+ struct radv_image *image,
+ const VkImageSubresourceRange *range, bool value);
void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image, bool value);
+ struct radv_image *image,
+ const VkImageSubresourceRange *range, bool value);
uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
struct radeon_winsys_bo *bo,
return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
}
+bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline);
+
struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
gl_shader_stage stage,
int idx);
int first_non_void);
uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
int first_non_void);
+bool radv_is_buffer_format_supported(VkFormat format, bool *scaled);
uint32_t radv_translate_colorformat(VkFormat format);
uint32_t radv_translate_color_numformat(VkFormat format,
const struct vk_format_description *desc,
unsigned slice_tile_max;
unsigned tile_mode_index;
unsigned tile_swizzle;
+ uint64_t slice_size;
};
struct radv_cmask_info {
uint64_t size;
unsigned alignment;
unsigned slice_tile_max;
+ unsigned slice_size;
};
uint64_t dcc_offset;
uint64_t htile_offset;
bool tc_compatible_htile;
+ bool tc_compatible_cmask;
struct radv_fmask_info fmask;
struct radv_cmask_info cmask;
return image->planes[0].surface.dcc_size;
}
+/**
+ * Return whether the image is TC-compatible CMASK.
+ */
+static inline bool
+radv_image_is_tc_compat_cmask(const struct radv_image *image)
+{
+ return radv_image_has_fmask(image) && image->tc_compatible_cmask;
+}
+
/**
* Return whether DCC metadata is enabled for a level.
*/
return radv_image_has_htile(image) && image->tc_compatible_htile;
}
+static inline uint64_t
+radv_image_get_fast_clear_va(const struct radv_image *image,
+ uint32_t base_level)
+{
+ uint64_t va = radv_buffer_get_va(image->bo);
+ va += image->offset + image->clear_value_offset + base_level * 8;
+ return va;
+}
+
+static inline uint64_t
+radv_image_get_fce_pred_va(const struct radv_image *image,
+ uint32_t base_level)
+{
+ uint64_t va = radv_buffer_get_va(image->bo);
+ va += image->offset + image->fce_pred_offset + base_level * 8;
+ return va;
+}
+
+static inline uint64_t
+radv_image_get_dcc_pred_va(const struct radv_image *image,
+ uint32_t base_level)
+{
+ uint64_t va = radv_buffer_get_va(image->bo);
+ va += image->offset + image->dcc_pred_offset + base_level * 8;
+ return va;
+}
+
unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
static inline uint32_t
const VkImageCreateInfo *vk_info;
bool scanout;
bool no_metadata_planes;
+ const struct radeon_bo_metadata *bo_metadata;
};
VkResult radv_image_create(VkDevice _device,
uint32_t cb_color_view;
uint32_t cb_color_info;
uint32_t cb_color_attrib;
- uint32_t cb_color_attrib2;
+ uint32_t cb_color_attrib2; /* GFX9 and later */
+ uint32_t cb_color_attrib3; /* GFX10 and later */
uint32_t cb_dcc_control;
uint32_t cb_color_cmask_slice;
uint32_t cb_color_fmask_slice;
uint32_t db_depth_slice;
uint32_t db_htile_surface;
uint32_t pa_su_poly_offset_db_fmt_cntl;
- uint32_t db_z_info2;
- uint32_t db_stencil_info2;
+ uint32_t db_z_info2; /* GFX9 only */
+ uint32_t db_stencil_info2; /* GFX9 only */
float offset_scale;
};
struct radv_subpass_attachment * color_attachments;
struct radv_subpass_attachment * resolve_attachments;
struct radv_subpass_attachment * depth_stencil_attachment;
+ struct radv_subpass_attachment * ds_resolve_attachment;
+ VkResolveModeFlagBitsKHR depth_resolve_mode;
+ VkResolveModeFlagBitsKHR stencil_resolve_mode;
- /** Subpass has at least one resolve attachment */
- bool has_resolve;
+ /** Subpass has at least one color resolve attachment */
+ bool has_color_resolve;
/** Subpass has at least one color attachment */
bool has_color_att;
VkSampleCountFlagBits max_sample_count;
};
+uint32_t
+radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer);
+
struct radv_render_pass_attachment {
VkFormat format;
uint32_t samples;
VkImageLayout initial_layout;
VkImageLayout final_layout;
- /* The subpass id in which the attachment will be used last. */
+ /* The subpass id in which the attachment will be used first/last. */
+ uint32_t first_subpass_idx;
uint32_t last_subpass_idx;
};
const VkWriteDescriptorSet *pDescriptorWrites);
void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image, uint32_t value);
+ struct radv_image *image,
+ const VkImageSubresourceRange *range, uint32_t value);
void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image);
+ struct radv_image *image,
+ const VkImageSubresourceRange *range);
struct radv_fence {
struct radeon_winsys_fence *fence;
struct wsi_fence *fence_wsi;
- bool submitted;
- bool signalled;
uint32_t syncobj;
uint32_t temp_syncobj;
void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
struct nir_shader *geom_shader,
- struct ac_shader_binary *binary,
- struct ac_shader_config *config,
+ struct radv_shader_binary **rbinary,
struct radv_shader_variant_info *shader_info,
const struct radv_nir_compiler_options *option);
void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
- struct ac_shader_binary *binary,
- struct ac_shader_config *config,
+ struct radv_shader_binary **rbinary,
struct radv_shader_variant_info *shader_info,
struct nir_shader *const *nir,
int nir_count,
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