#include "ac_llvm_util.h"
#include "radv_descriptor_set.h"
#include "radv_extensions.h"
-#include "radv_cs.h"
+#include "sid.h"
#include <llvm-c/TargetMachine.h>
#include "wsi_common.h"
#include "wsi_common_display.h"
+struct gfx10_format {
+ unsigned img_format:9;
+
+ /* Various formats are only supported with workarounds for vertex fetch,
+ * and some 32_32_32 formats are supported natively, but only for buffers
+ * (possibly with some image support, actually, but no filtering). */
+ bool buffers_only:1;
+};
+
+#include "gfx10_format_table.h"
+
#define ATI_VENDOR_ID 0x1002
#define MAX_VBS 32
uint32_t optimisations_disabled : 1;
};
+struct radv_shader_binary;
+struct radv_shader_variant;
+
void
radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
struct radv_device *device);
radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
const void *data, size_t size);
-struct radv_shader_variant;
-
bool
radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
struct radv_pipeline_cache *cache,
struct radv_pipeline_cache *cache,
const unsigned char *sha1,
struct radv_shader_variant **variants,
- const void *const *codes,
- const unsigned *code_sizes);
+ struct radv_shader_binary *const *binaries);
enum radv_blit_ds_layout {
RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
};
enum radv_cmd_flush_bits {
- RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
- /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
- RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
- /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
- RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
- /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
- RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
- /* Same as above, but only writes back and doesn't invalidate */
- RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
+ /* Instruction cache. */
+ RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
+ /* Scalar L1 cache. */
+ RADV_CMD_FLAG_INV_SCACHE = 1 << 1,
+ /* Vector L1 cache. */
+ RADV_CMD_FLAG_INV_VCACHE = 1 << 2,
+ /* L2 cache + L2 metadata cache writeback & invalidate.
+ * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
+ RADV_CMD_FLAG_INV_L2 = 1 << 3,
+ /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
+ * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
+ * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
+ RADV_CMD_FLAG_WB_L2 = 1 << 4,
/* Framebuffer caches */
- RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
- RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
- RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
- RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
+ RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
+ RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
+ RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
+ RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
/* Engine synchronization. */
- RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
- RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
- RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
- RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
+ RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
+ RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
+ RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
+ RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
/* Pipeline query controls. */
- RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
- RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
- RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
+ RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
+ RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
+ RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
}
+bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline);
+
struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
gl_shader_stage stage,
int idx);
uint32_t cb_color_view;
uint32_t cb_color_info;
uint32_t cb_color_attrib;
- uint32_t cb_color_attrib2;
+ uint32_t cb_color_attrib2; /* GFX9 and later */
+ uint32_t cb_color_attrib3; /* GFX10 and later */
uint32_t cb_dcc_control;
uint32_t cb_color_cmask_slice;
uint32_t cb_color_fmask_slice;
uint32_t db_depth_slice;
uint32_t db_htile_surface;
uint32_t pa_su_poly_offset_db_fmt_cntl;
- uint32_t db_z_info2;
- uint32_t db_stencil_info2;
+ uint32_t db_z_info2; /* GFX9 only */
+ uint32_t db_stencil_info2; /* GFX9 only */
float offset_scale;
};
void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
struct nir_shader *geom_shader,
- struct ac_shader_binary *binary,
- struct ac_shader_config *config,
+ struct radv_shader_binary **rbinary,
struct radv_shader_variant_info *shader_info,
const struct radv_nir_compiler_options *option);
void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
- struct ac_shader_binary *binary,
- struct ac_shader_config *config,
+ struct radv_shader_binary **rbinary,
struct radv_shader_variant_info *shader_info,
struct nir_shader *const *nir,
int nir_count,
projects / mesa.git / blobdiff