radv: set correct INDEX_TYPE for indexed indirect draws on GFX9

[mesa.git] / src / amd / vulkan / radv_query.c

diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index 910eedd833cc38ed7094dd0e65bb165657b17310..06045d6b41bfa9e542fa0018b44102eb63e6c0f6 100644 (file)
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -44,11 +44,6 @@ static unsigned get_max_db(struct radv_device *device)
        unsigned num_db = device->physical_device->rad_info.num_render_backends;
        MAYBE_UNUSED unsigned rb_mask = device->physical_device->rad_info.enabled_rb_mask;
 
-       if (device->physical_device->rad_info.chip_class == SI)
-               num_db = 8;
-       else
-               num_db = MAX2(8, num_db);
-
        /* Otherwise we need to change the query reset procedure */
        assert(rb_mask == ((1ull << num_db) - 1));
 
@@ -524,8 +519,6 @@ VkResult radv_device_init_meta_query_state(struct radv_device *device)
        struct radv_shader_module occlusion_cs = { .nir = NULL };
        struct radv_shader_module pipeline_statistics_cs = { .nir = NULL };
 
-       zero(device->meta_state.query);
-
        occlusion_cs.nir = build_occlusion_query_shader(device);
        pipeline_statistics_cs.nir = build_pipeline_statistics_query_shader(device);
 
@@ -656,9 +649,12 @@ static void radv_query_shader(struct radv_cmd_buffer *cmd_buffer,
                               uint32_t pipeline_stats_mask, uint32_t avail_offset)
 {
        struct radv_device *device = cmd_buffer->device;
-       struct radv_meta_saved_compute_state saved_state;
+       struct radv_meta_saved_state saved_state;
 
-       radv_meta_save_compute(&saved_state, cmd_buffer, 4);
+       radv_meta_save(&saved_state, cmd_buffer,
+                      RADV_META_SAVE_COMPUTE_PIPELINE |
+                      RADV_META_SAVE_CONSTANTS |
+                      RADV_META_SAVE_DESCRIPTORS);
 
        struct radv_buffer dst_buffer = {
                .bo = dst_bo,
@@ -742,7 +738,7 @@ static void radv_query_shader(struct radv_cmd_buffer *cmd_buffer,
                                        RADV_CMD_FLAG_INV_VMEM_L1 |
                                        RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
 
-       radv_meta_restore_compute(&saved_state, cmd_buffer, 4);
+       radv_meta_restore(&saved_state, cmd_buffer);
 }
 
 VkResult radv_CreateQueryPool(
@@ -957,8 +953,8 @@ void radv_CmdCopyQueryPoolResults(
        RADV_FROM_HANDLE(radv_buffer, dst_buffer, dstBuffer);
        struct radeon_winsys_cs *cs = cmd_buffer->cs;
        unsigned elem_size = (flags & VK_QUERY_RESULT_64_BIT) ? 8 : 4;
-       uint64_t va = cmd_buffer->device->ws->buffer_get_va(pool->bo);
-       uint64_t dest_va = cmd_buffer->device->ws->buffer_get_va(dst_buffer->bo);
+       uint64_t va = radv_buffer_get_va(pool->bo);
+       uint64_t dest_va = radv_buffer_get_va(dst_buffer->bo);
        dest_va += dst_buffer->offset + dstOffset;
 
        cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, pool->bo, 8);
@@ -997,7 +993,7 @@ void radv_CmdCopyQueryPoolResults(
                                uint64_t avail_va = va + pool->availability_offset + 4 * query;
 
                                /* This waits on the ME. All copies below are done on the ME */
-                               si_emit_wait_fence(cs, avail_va, 1, 0xffffffff);
+                               si_emit_wait_fence(cs, false, avail_va, 1, 0xffffffff);
                        }
                }
                radv_query_shader(cmd_buffer, cmd_buffer->device->meta_state.query.pipeline_statistics_query_pipeline,
@@ -1020,7 +1016,7 @@ void radv_CmdCopyQueryPoolResults(
                                uint64_t avail_va = va + pool->availability_offset + 4 * query;
 
                                /* This waits on the ME. All copies below are done on the ME */
-                               si_emit_wait_fence(cs, avail_va, 1, 0xffffffff);
+                               si_emit_wait_fence(cs, false, avail_va, 1, 0xffffffff);
                        }
                        if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
                                uint64_t avail_va = va + pool->availability_offset + 4 * query;
@@ -1062,7 +1058,7 @@ void radv_CmdResetQueryPool(
 {
        RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
        RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
-       uint64_t va = cmd_buffer->device->ws->buffer_get_va(pool->bo);
+       uint64_t va = radv_buffer_get_va(pool->bo);
 
        cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, pool->bo, 8);
 
@@ -1083,7 +1079,7 @@ void radv_CmdBeginQuery(
        RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
        RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
        struct radeon_winsys_cs *cs = cmd_buffer->cs;
-       uint64_t va = cmd_buffer->device->ws->buffer_get_va(pool->bo);
+       uint64_t va = radv_buffer_get_va(pool->bo);
        va += pool->stride * query;
 
        cmd_buffer->device->ws->cs_add_buffer(cs, pool->bo, 8);
@@ -1123,7 +1119,7 @@ void radv_CmdEndQuery(
        RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
        RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
        struct radeon_winsys_cs *cs = cmd_buffer->cs;
-       uint64_t va = cmd_buffer->device->ws->buffer_get_va(pool->bo);
+       uint64_t va = radv_buffer_get_va(pool->bo);
        uint64_t avail_va = va + pool->availability_offset + 4 * query;
        va += pool->stride * query;
 
@@ -1144,7 +1140,7 @@ void radv_CmdEndQuery(
 
                break;
        case VK_QUERY_TYPE_PIPELINE_STATISTICS:
-               radeon_check_space(cmd_buffer->device->ws, cs, 10);
+               radeon_check_space(cmd_buffer->device->ws, cs, 16);
 
                va += pipelinestat_block_size;
 
@@ -1153,13 +1149,12 @@ void radv_CmdEndQuery(
                radeon_emit(cs, va);
                radeon_emit(cs, va >> 32);
 
-               radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
-               radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
-                               EVENT_INDEX(5));
-               radeon_emit(cs, avail_va);
-               radeon_emit(cs, (avail_va >> 32) | EOP_DATA_SEL(1));
-               radeon_emit(cs, 1);
-               radeon_emit(cs, 0);
+               si_cs_emit_write_event_eop(cs,
+                                          false,
+                                          cmd_buffer->device->physical_device->rad_info.chip_class,
+                                          false,
+                                          V_028A90_BOTTOM_OF_PIPE_TS, 0,
+                                          1, avail_va, 0, 1);
                break;
        default:
                unreachable("ending unhandled query type");
@@ -1176,13 +1171,13 @@ void radv_CmdWriteTimestamp(
        RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
        bool mec = radv_cmd_buffer_uses_mec(cmd_buffer);
        struct radeon_winsys_cs *cs = cmd_buffer->cs;
-       uint64_t va = cmd_buffer->device->ws->buffer_get_va(pool->bo);
+       uint64_t va = radv_buffer_get_va(pool->bo);
        uint64_t avail_va = va + pool->availability_offset + 4 * query;
        uint64_t query_va = va + pool->stride * query;
 
        cmd_buffer->device->ws->cs_add_buffer(cs, pool->bo, 5);
 
-       MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 14);
+       MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 28);
 
        switch(pipelineStage) {
        case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT:
@@ -1204,37 +1199,18 @@ void radv_CmdWriteTimestamp(
                radeon_emit(cs, 1);
                break;
        default:
-               if (mec) {
-                       radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 5, 0));
-                       radeon_emit(cs, EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5));
-                       radeon_emit(cs, 3 << 29);
-                       radeon_emit(cs, query_va);
-                       radeon_emit(cs, query_va >> 32);
-                       radeon_emit(cs, 0);
-                       radeon_emit(cs, 0);
-
-                       radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 5, 0));
-                       radeon_emit(cs, EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5));
-                       radeon_emit(cs, 1 << 29);
-                       radeon_emit(cs, avail_va);
-                       radeon_emit(cs, avail_va >> 32);
-                       radeon_emit(cs, 1);
-                       radeon_emit(cs, 0);
-               } else {
-                       radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
-                       radeon_emit(cs, EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5));
-                       radeon_emit(cs, query_va);
-                       radeon_emit(cs, (3 << 29) | ((query_va >> 32) & 0xFFFF));
-                       radeon_emit(cs, 0);
-                       radeon_emit(cs, 0);
-
-                       radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
-                       radeon_emit(cs, EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5));
-                       radeon_emit(cs, avail_va);
-                       radeon_emit(cs, (1 << 29) | ((avail_va >> 32) & 0xFFFF));
-                       radeon_emit(cs, 1);
-                       radeon_emit(cs, 0);
-               }
+               si_cs_emit_write_event_eop(cs,
+                                          false,
+                                          cmd_buffer->device->physical_device->rad_info.chip_class,
+                                          mec,
+                                          V_028A90_BOTTOM_OF_PIPE_TS, 0,
+                                          3, query_va, 0, 0);
+               si_cs_emit_write_event_eop(cs,
+                                          false,
+                                          cmd_buffer->device->physical_device->rad_info.chip_class,
+                                          mec,
+                                          V_028A90_BOTTOM_OF_PIPE_TS, 0,
+                                          1, avail_va, 0, 1);
                break;
        }