radv/gfx9: allocate events from uncached VA space

[mesa.git] / src / amd / vulkan / radv_query.c

diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index 6d05612579f4e723589216d77981383cdd85efef..3c40774042dd67b43ae4f07a0fdeabc9bb7893fd 100644 (file)
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -44,9 +44,6 @@ static unsigned get_max_db(struct radv_device *device)
        unsigned num_db = device->physical_device->rad_info.num_render_backends;
        MAYBE_UNUSED unsigned rb_mask = device->physical_device->rad_info.enabled_rb_mask;
 
-       if (device->physical_device->rad_info.chip_class == SI)
-               num_db = 8;
-
        /* Otherwise we need to change the query reset procedure */
        assert(rb_mask == ((1ull << num_db) - 1));
 
@@ -995,7 +992,7 @@ void radv_CmdCopyQueryPoolResults(
                                uint64_t avail_va = va + pool->availability_offset + 4 * query;
 
                                /* This waits on the ME. All copies below are done on the ME */
-                               si_emit_wait_fence(cs, avail_va, 1, 0xffffffff);
+                               si_emit_wait_fence(cs, false, avail_va, 1, 0xffffffff);
                        }
                }
                radv_query_shader(cmd_buffer, cmd_buffer->device->meta_state.query.pipeline_statistics_query_pipeline,
@@ -1018,7 +1015,7 @@ void radv_CmdCopyQueryPoolResults(
                                uint64_t avail_va = va + pool->availability_offset + 4 * query;
 
                                /* This waits on the ME. All copies below are done on the ME */
-                               si_emit_wait_fence(cs, avail_va, 1, 0xffffffff);
+                               si_emit_wait_fence(cs, false, avail_va, 1, 0xffffffff);
                        }
                        if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
                                uint64_t avail_va = va + pool->availability_offset + 4 * query;
@@ -1152,6 +1149,7 @@ void radv_CmdEndQuery(
                radeon_emit(cs, va >> 32);
 
                si_cs_emit_write_event_eop(cs,
+                                          false,
                                           cmd_buffer->device->physical_device->rad_info.chip_class,
                                           false,
                                           EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
@@ -1201,11 +1199,13 @@ void radv_CmdWriteTimestamp(
                break;
        default:
                si_cs_emit_write_event_eop(cs,
+                                          false,
                                           cmd_buffer->device->physical_device->rad_info.chip_class,
                                           mec,
                                           V_028A90_BOTTOM_OF_PIPE_TS, 0,
                                           3, query_va, 0, 0);
                si_cs_emit_write_event_eop(cs,
+                                          false,
                                           cmd_buffer->device->physical_device->rad_info.chip_class,
                                           mec,
                                           V_028A90_BOTTOM_OF_PIPE_TS, 0,