radv: Add support for ETC2 textures.

[mesa.git] / src / amd / vulkan / radv_query.c

diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index 559b7cd49dcd8845874fe28fc5b891d2477dfa29..e3229ab59bbe827ab5364361cc44ce0abbaad0cf 100644 (file)
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -188,10 +188,8 @@ build_occlusion_query_shader(struct radv_device *device) {
        load->num_components = 2;
        nir_builder_instr_insert(&b, &load->instr);
 
-       const unsigned swizzle0[] = {0,0,0,0};
-       const unsigned swizzle1[] = {1,1,1,1};
-       nir_store_var(&b, start, nir_swizzle(&b, &load->dest.ssa, swizzle0, 1, false), 0x1);
-       nir_store_var(&b, end, nir_swizzle(&b, &load->dest.ssa, swizzle1, 1, false), 0x1);
+       nir_store_var(&b, start, nir_channel(&b, &load->dest.ssa, 0), 0x1);
+       nir_store_var(&b, end, nir_channel(&b, &load->dest.ssa, 1), 0x1);
 
        nir_ssa_def *start_done = nir_ilt(&b, nir_load_var(&b, start), nir_imm_int64(&b, 0));
        nir_ssa_def *end_done = nir_ilt(&b, nir_load_var(&b, end), nir_imm_int64(&b, 0));
@@ -956,8 +954,8 @@ void radv_CmdCopyQueryPoolResults(
        uint64_t dest_va = radv_buffer_get_va(dst_buffer->bo);
        dest_va += dst_buffer->offset + dstOffset;
 
-       radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, pool->bo, 8);
-       radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, dst_buffer->bo, 8);
+       radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, pool->bo);
+       radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, dst_buffer->bo);
 
        switch (pool->type) {
        case VK_QUERY_TYPE_OCCLUSION:
@@ -992,7 +990,7 @@ void radv_CmdCopyQueryPoolResults(
                                uint64_t avail_va = va + pool->availability_offset + 4 * query;
 
                                /* This waits on the ME. All copies below are done on the ME */
-                               si_emit_wait_fence(cs, false, avail_va, 1, 0xffffffff);
+                               si_emit_wait_fence(cs, avail_va, 1, 0xffffffff);
                        }
                }
                radv_query_shader(cmd_buffer, cmd_buffer->device->meta_state.query.pipeline_statistics_query_pipeline,
@@ -1015,7 +1013,7 @@ void radv_CmdCopyQueryPoolResults(
                                uint64_t avail_va = va + pool->availability_offset + 4 * query;
 
                                /* This waits on the ME. All copies below are done on the ME */
-                               si_emit_wait_fence(cs, false, avail_va, 1, 0xffffffff);
+                               si_emit_wait_fence(cs, avail_va, 1, 0xffffffff);
                        }
                        if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
                                uint64_t avail_va = va + pool->availability_offset + 4 * query;
@@ -1118,6 +1116,12 @@ static void emit_begin_query(struct radv_cmd_buffer *cmd_buffer,
        case VK_QUERY_TYPE_PIPELINE_STATISTICS:
                radeon_check_space(cmd_buffer->device->ws, cs, 4);
 
+               ++cmd_buffer->state.active_pipeline_queries;
+               if (cmd_buffer->state.active_pipeline_queries == 1) {
+                       cmd_buffer->state.flush_bits &= ~RADV_CMD_FLAG_STOP_PIPELINE_STATS;
+                       cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_START_PIPELINE_STATS;
+               }
+
                radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
                radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
                radeon_emit(cs, va);
@@ -1157,6 +1161,11 @@ static void emit_end_query(struct radv_cmd_buffer *cmd_buffer,
        case VK_QUERY_TYPE_PIPELINE_STATISTICS:
                radeon_check_space(cmd_buffer->device->ws, cs, 16);
 
+               cmd_buffer->state.active_pipeline_queries--;
+               if (cmd_buffer->state.active_pipeline_queries == 0) {
+                       cmd_buffer->state.flush_bits &= ~RADV_CMD_FLAG_START_PIPELINE_STATS;
+                       cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_STOP_PIPELINE_STATS;
+               }
                va += pipelinestat_block_size;
 
                radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
@@ -1165,11 +1174,12 @@ static void emit_end_query(struct radv_cmd_buffer *cmd_buffer,
                radeon_emit(cs, va >> 32);
 
                si_cs_emit_write_event_eop(cs,
-                                          false,
                                           cmd_buffer->device->physical_device->rad_info.chip_class,
                                           radv_cmd_buffer_uses_mec(cmd_buffer),
                                           V_028A90_BOTTOM_OF_PIPE_TS, 0,
-                                          1, avail_va, 0, 1);
+                                          EOP_DATA_SEL_VALUE_32BIT,
+                                          avail_va, 0, 1,
+                                          cmd_buffer->gfx9_eop_bug_va);
                break;
        default:
                unreachable("ending unhandled query type");
@@ -1187,7 +1197,7 @@ void radv_CmdBeginQuery(
        struct radeon_cmdbuf *cs = cmd_buffer->cs;
        uint64_t va = radv_buffer_get_va(pool->bo);
 
-       radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo, 8);
+       radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo);
 
        if (cmd_buffer->pending_reset_query) {
                if (pool->size >= RADV_BUFFER_OPS_CS_THRESHOLD) {
@@ -1258,7 +1268,7 @@ void radv_CmdWriteTimestamp(
        uint64_t avail_va = va + pool->availability_offset + 4 * query;
        uint64_t query_va = va + pool->stride * query;
 
-       radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo, 5);
+       radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo);
 
        int num_queries = 1;
        if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask)
@@ -1288,17 +1298,19 @@ void radv_CmdWriteTimestamp(
                        break;
                default:
                        si_cs_emit_write_event_eop(cs,
-                                                  false,
                                                   cmd_buffer->device->physical_device->rad_info.chip_class,
                                                   mec,
                                                   V_028A90_BOTTOM_OF_PIPE_TS, 0,
-                                                  3, query_va, 0, 0);
+                                                  EOP_DATA_SEL_TIMESTAMP,
+                                                  query_va, 0, 0,
+                                                  cmd_buffer->gfx9_eop_bug_va);
                        si_cs_emit_write_event_eop(cs,
-                                                  false,
                                                   cmd_buffer->device->physical_device->rad_info.chip_class,
                                                   mec,
                                                   V_028A90_BOTTOM_OF_PIPE_TS, 0,
-                                                  1, avail_va, 0, 1);
+                                                  EOP_DATA_SEL_VALUE_32BIT,
+                                                  avail_va, 0, 1,
+                                                  cmd_buffer->gfx9_eop_bug_va);
                        break;
                }
                query_va += pool->stride;