radv: allow to set dynamic sample locations to the depth decompress pass

[mesa.git] / src / amd / vulkan / radv_shader.c

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 7568d59056cce149f7d7930e31fdfbbb1dd48dbe..37fdbfe33f53ef317a900e8c75ea51028066a3fc 100644 (file)
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -40,7 +40,6 @@
 #include <llvm-c/Support.h>
 
 #include "sid.h"
-#include "gfx9d.h"
 #include "ac_binary.h"
 #include "ac_llvm_util.h"
 #include "ac_nir_to_llvm.h"
@@ -150,7 +149,7 @@ radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
                NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
                NIR_PASS(progress, shader, nir_opt_dead_write_vars);
 
-                NIR_PASS_V(shader, nir_lower_alu_to_scalar);
+                NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL);
                 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
 
                 NIR_PASS(progress, shader, nir_copy_prop);
@@ -166,11 +165,11 @@ radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
                 NIR_PASS(progress, shader, nir_opt_dead_cf);
                 NIR_PASS(progress, shader, nir_opt_cse);
                 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
-                NIR_PASS(progress, shader, nir_opt_algebraic);
                 NIR_PASS(progress, shader, nir_opt_constant_folding);
+                NIR_PASS(progress, shader, nir_opt_algebraic);
 
                 if (lower_flrp != 0) {
-                        bool lower_flrp_progress;
+                        bool lower_flrp_progress = false;
                         NIR_PASS(lower_flrp_progress,
                                  shader,
                                  nir_lower_flrp,
@@ -210,7 +209,6 @@ radv_shader_compile_to_nir(struct radv_device *device,
                           const struct radv_pipeline_layout *layout)
 {
        nir_shader *nir;
-       nir_function *entry_point;
        if (module->nir) {
                /* Some things such as our meta clear/blit code will give us a NIR
                 * shader directly.  In that case, we just ignore the SPIR-V entirely
@@ -220,8 +218,6 @@ radv_shader_compile_to_nir(struct radv_device *device,
                nir_validate_shader(nir, "in internal shader");
 
                assert(exec_list_length(&nir->functions) == 1);
-               struct exec_node *node = exec_list_get_head(&nir->functions);
-               entry_point = exec_node_data(nir_function, node, node);
        } else {
                uint32_t *spirv = (uint32_t *) module->data;
                assert(module->size % 4 == 0);
@@ -284,17 +280,16 @@ radv_shader_compile_to_nir(struct radv_device *device,
                                .trinary_minmax = true,
                                .variable_pointers = true,
                        },
-                       .ubo_ptr_type = glsl_vector_type(GLSL_TYPE_UINT, 2),
-                       .ssbo_ptr_type = glsl_vector_type(GLSL_TYPE_UINT, 2),
-                       .phys_ssbo_ptr_type = glsl_vector_type(GLSL_TYPE_UINT64, 1),
-                       .push_const_ptr_type = glsl_uint_type(),
-                       .shared_ptr_type = glsl_uint_type(),
+                       .ubo_addr_format = nir_address_format_32bit_index_offset,
+                       .ssbo_addr_format = nir_address_format_32bit_index_offset,
+                       .phys_ssbo_addr_format = nir_address_format_64bit_global,
+                       .push_const_addr_format = nir_address_format_logical,
+                       .shared_addr_format = nir_address_format_32bit_offset,
                };
-               entry_point = spirv_to_nir(spirv, module->size / 4,
-                                          spec_entries, num_spec_entries,
-                                          stage, entrypoint_name,
-                                          &spirv_options, &nir_options);
-               nir = entry_point->shader;
+               nir = spirv_to_nir(spirv, module->size / 4,
+                                  spec_entries, num_spec_entries,
+                                  stage, entrypoint_name,
+                                  &spirv_options, &nir_options);
                assert(nir->info.stage == stage);
                nir_validate_shader(nir, "after spirv_to_nir");
 
@@ -311,11 +306,12 @@ radv_shader_compile_to_nir(struct radv_device *device,
 
                /* Pick off the single entrypoint that we want */
                foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
-                       if (func != entry_point)
+                       if (func->is_entrypoint)
+                               func->name = ralloc_strdup(func, "main");
+                       else
                                exec_node_remove(&func->node);
                }
                assert(exec_list_length(&nir->functions) == 1);
-               entry_point->name = ralloc_strdup(entry_point, "main");
 
                /* Make sure we lower constant initializers on output variables so that
                 * nir_remove_dead_variables below sees the corresponding stores
@@ -344,7 +340,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
        /* Vulkan uses the separate-shader linking model */
        nir->info.separate_shader = true;
 
-       nir_shader_gather_info(nir, entry_point->impl);
+       nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 
        static const nir_lower_tex_options tex_options = {
          .lower_txp = ~0,
@@ -649,6 +645,8 @@ shader_variant_create(struct radv_device *device,
                tm_options |= AC_TM_SISCHED;
        if (options->check_ir)
                tm_options |= AC_TM_CHECK_IR;
+       if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
+               tm_options |= AC_TM_NO_LOAD_STORE_OPT;
 
        thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
        radv_init_llvm_once();
@@ -773,7 +771,7 @@ generate_shader_stats(struct radv_device *device,
                      struct _mesa_string_buffer *buf)
 {
        enum chip_class chip_class = device->physical_device->rad_info.chip_class;
-       unsigned lds_increment = chip_class >= CIK ? 512 : 256;
+       unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
        struct ac_shader_config *conf;
        unsigned max_simd_waves;
        unsigned lds_per_wave = 0;
@@ -875,7 +873,7 @@ radv_GetShaderInfoAMD(VkDevice _device,
                if (!pInfo) {
                        *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
                } else {
-                       unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
+                       unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
                        struct ac_shader_config *conf = &variant->config;
 
                        VkShaderStatisticsInfoAMD statistics = {};