radv: Fix uninitialized warning.

[mesa.git] / src / amd / vulkan / radv_shader.c

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index bcc050a86ccd04036b8cfc1d96180480dc14ec1d..4262dae28607bbe120946476ebc97904c26d2e21 100644 (file)
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -810,7 +810,8 @@ static void radv_postprocess_config(const struct radv_physical_device *pdevice,
                } else if (es_stage == MESA_SHADER_TESS_EVAL) {
                        bool enable_prim_id = info->tes.export_prim_id || info->info.uses_prim_id;
                        es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
-               }
+               } else
+                       unreachable("Unexpected ES shader stage");
 
                bool tes_triangles = stage == MESA_SHADER_TESS_EVAL &&
                        info->tes.primitive_mode >= 4; /* GL_TRIANGLES */
@@ -961,6 +962,7 @@ radv_shader_variant_create(struct radv_device *device,
                struct ac_rtld_open_info open_info = {
                        .info = &device->physical_device->rad_info,
                        .shader_type = binary->stage,
+                       .wave_size = 64,
                        .num_parts = 1,
                        .elf_ptrs = &elf_data,
                        .elf_sizes = &elf_size,
@@ -1011,18 +1013,20 @@ radv_shader_variant_create(struct radv_device *device,
                        return NULL;
                }
 
-               const char *disasm_data;
-               size_t disasm_size;
-               if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
-                       radv_shader_variant_destroy(device, variant);
-                       ac_rtld_close(&rtld_binary);
-                       return NULL;
-               }
+               if (device->keep_shader_info) {
+                       const char *disasm_data;
+                       size_t disasm_size;
+                       if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
+                               radv_shader_variant_destroy(device, variant);
+                               ac_rtld_close(&rtld_binary);
+                               return NULL;
+                       }
 
-               variant->llvm_ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
-               variant->disasm_string = malloc(disasm_size + 1);
-               memcpy(variant->disasm_string, disasm_data, disasm_size);
-               variant->disasm_string[disasm_size] = 0;
+                       variant->llvm_ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
+                       variant->disasm_string = malloc(disasm_size + 1);
+                       memcpy(variant->disasm_string, disasm_data, disasm_size);
+                       variant->disasm_string[disasm_size] = 0;
+               }
 
                ac_rtld_close(&rtld_binary);
        } else {
@@ -1232,7 +1236,7 @@ generate_shader_stats(struct radv_device *device,
                                     lds_increment);
        } else if (stage == MESA_SHADER_COMPUTE) {
                unsigned max_workgroup_size =
-                               radv_nir_get_max_workgroup_size(chip_class, variant->nir);
+                       radv_nir_get_max_workgroup_size(chip_class, stage, variant->nir);
                lds_per_wave = (conf->lds_size * lds_increment) /
                               DIV_ROUND_UP(max_workgroup_size, 64);
        }