radv/gfx9: enable LDS for GS only if the ES type is TES

[mesa.git] / src / amd / vulkan / radv_shader.c

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 4a3fdfa80ec918d54328fd067cf19a4f4b6861b0..58d991e4526ee8abd72f2559f236b74f17e7a080 100644 (file)
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -330,7 +330,10 @@ radv_alloc_shader_memory(struct radv_device *device,
 
        slab->size = 256 * 1024;
        slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
-                                            RADEON_DOMAIN_VRAM, RADEON_FLAG_NO_INTERPROCESS_SHARING);
+                                            RADEON_DOMAIN_VRAM,
+                                            RADEON_FLAG_NO_INTERPROCESS_SHARING |
+                                            device->physical_device->cpdma_prefetch_writes_memory ?
+                                                    0 : RADEON_FLAG_READ_ONLY);
        slab->ptr = (char*)device->ws->buffer_map(slab->bo);
        list_inithead(&slab->shaders);
 
@@ -392,13 +395,18 @@ radv_fill_shader_variant(struct radv_device *device,
                break;
        case MESA_SHADER_FRAGMENT:
                break;
-       case MESA_SHADER_COMPUTE:
+       case MESA_SHADER_COMPUTE: {
+               struct ac_shader_info *info = &variant->info.info;
                variant->rsrc2 |=
-                       S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
-                       S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
-                       S_00B84C_TG_SIZE_EN(1) |
+                       S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
+                       S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
+                       S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
+                       S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
+                                               info->cs.uses_thread_id[1] ? 1 : 0) |
+                       S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
                        S_00B84C_LDS_SIZE(variant->config.lds_size);
                break;
+       }
        default:
                unreachable("unsupported shader type");
                break;
@@ -406,10 +414,26 @@ radv_fill_shader_variant(struct radv_device *device,
 
        if (device->physical_device->rad_info.chip_class >= GFX9 &&
            stage == MESA_SHADER_GEOMETRY) {
+               struct ac_shader_info *info = &variant->info.info;
+               unsigned es_type = variant->info.gs.es_type;
+               unsigned gs_vgpr_comp_cnt;
+
+               /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
+                * VGPR[0:4] are always loaded.
+                */
+               if (info->uses_invocation_id)
+                       gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
+               else if (info->uses_prim_id)
+                       gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
+               else if (variant->info.gs.vertices_in >= 3)
+                       gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
+               else
+                       gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
+
                /* TODO: Figure out how many we actually need. */
-               variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(3);
+               variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
                variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(3) |
-                                 S_00B22C_OC_LDS_EN(1);
+                                 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
        } else if (device->physical_device->rad_info.chip_class >= GFX9 &&
            stage == MESA_SHADER_TESS_CTRL)
                variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);