ac: move ac_shader_info to radv folder

[mesa.git] / src / amd / vulkan / radv_shader.c

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 620effe50e6b4e9bc918e2a3c7aeafb5802f7568..e11f19323f7e5716aad855342c82d4a1781d6616 100644 (file)
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -53,6 +53,7 @@ static const struct nir_shader_compiler_options nir_options = {
        .lower_scmp = true,
        .lower_flrp32 = true,
        .lower_flrp64 = true,
+       .lower_device_index_to_zero = true,
        .lower_fsat = true,
        .lower_fdiv = true,
        .lower_sub = true,
@@ -67,6 +68,8 @@ static const struct nir_shader_compiler_options nir_options = {
        .lower_extract_byte = true,
        .lower_extract_word = true,
        .lower_ffma = true,
+       .lower_fpow = true,
+       .vs_inputs_dual_locations = true,
        .max_unroll_iterations = 32
 };
 
@@ -147,6 +150,8 @@ radv_optimize_nir(struct nir_shader *shader)
                         NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
                 }
         } while (progress);
+
+        NIR_PASS(progress, shader, nir_opt_shrink_load);
 }
 
 nir_shader *
@@ -199,6 +204,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
                }
                const struct spirv_to_nir_options spirv_options = {
                        .caps = {
+                               .device_group = true,
                                .draw_parameters = true,
                                .float64 = true,
                                .image_read_without_format = true,
@@ -206,8 +212,12 @@ radv_shader_compile_to_nir(struct radv_device *device,
                                .tessellation = true,
                                .int64 = true,
                                .multiview = true,
+                               .subgroup_basic = true,
                                .variable_pointers = true,
                        },
+                       .exts = {
+                               .AMD_gcn_shader = true,
+                       },
                };
                entry_point = spirv_to_nir(spirv, module->size / 4,
                                           spec_entries, num_spec_entries,
@@ -251,40 +261,6 @@ radv_shader_compile_to_nir(struct radv_device *device,
 
        nir_shader_gather_info(nir, entry_point->impl);
 
-       /* While it would be nice not to have this flag, we are constrained
-        * by the reality that LLVM 5.0 doesn't have working VGPR indexing
-        * on GFX9.
-        */
-       bool llvm_has_working_vgpr_indexing =
-               device->physical_device->rad_info.chip_class <= VI;
-
-       /* TODO: Indirect indexing of GS inputs is unimplemented.
-        *
-        * TCS and TES load inputs directly from LDS or offchip memory, so
-        * indirect indexing is trivial.
-        */
-       nir_variable_mode indirect_mask = 0;
-       if (nir->info.stage == MESA_SHADER_GEOMETRY ||
-           (nir->info.stage != MESA_SHADER_TESS_CTRL &&
-            nir->info.stage != MESA_SHADER_TESS_EVAL &&
-            !llvm_has_working_vgpr_indexing)) {
-               indirect_mask |= nir_var_shader_in;
-       }
-       if (!llvm_has_working_vgpr_indexing &&
-           nir->info.stage != MESA_SHADER_TESS_CTRL)
-               indirect_mask |= nir_var_shader_out;
-
-       /* TODO: We shouldn't need to do this, however LLVM isn't currently
-        * smart enough to handle indirects without causing excess spilling
-        * causing the gpu to hang.
-        *
-        * See the following thread for more details of the problem:
-        * https://lists.freedesktop.org/archives/mesa-dev/2017-July/162106.html
-        */
-       indirect_mask |= nir_var_local;
-
-       nir_lower_indirect_derefs(nir, indirect_mask);
-
        static const nir_lower_tex_options tex_options = {
          .lower_txp = ~0,
        };
@@ -295,6 +271,16 @@ radv_shader_compile_to_nir(struct radv_device *device,
        nir_lower_var_copies(nir);
        nir_lower_global_vars_to_local(nir);
        nir_remove_dead_variables(nir, nir_var_local);
+       ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
+       nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
+                       .subgroup_size = 64,
+                       .ballot_bit_size = 64,
+                       .lower_to_scalar = 1,
+                       .lower_subgroup_masks = 1,
+                       .lower_shuffle = 1,
+                       .lower_quad =  1,
+               });
+
        radv_optimize_nir(nir);
 
        return nir;
@@ -397,7 +383,7 @@ radv_fill_shader_variant(struct radv_device *device,
        case MESA_SHADER_FRAGMENT:
                break;
        case MESA_SHADER_COMPUTE: {
-               struct ac_shader_info *info = &variant->info.info;
+               struct radv_shader_info *info = &variant->info.info;
                variant->rsrc2 |=
                        S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
                        S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
@@ -415,7 +401,7 @@ radv_fill_shader_variant(struct radv_device *device,
 
        if (device->physical_device->rad_info.chip_class >= GFX9 &&
            stage == MESA_SHADER_GEOMETRY) {
-               struct ac_shader_info *info = &variant->info.info;
+               struct radv_shader_info *info = &variant->info.info;
                unsigned es_type = variant->info.gs.es_type;
                unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
 
@@ -487,12 +473,13 @@ shader_variant_create(struct radv_device *device,
 
        if (gs_copy_shader) {
                assert(shader_count == 1);
-               ac_create_gs_copy_shader(tm, *shaders, &binary, &variant->config,
-                                        &variant->info, options, dump_shaders);
+               radv_compile_gs_copy_shader(tm, *shaders, &binary,
+                                           &variant->config, &variant->info,
+                                           options, dump_shaders);
        } else {
-               ac_compile_nir_shader(tm, &binary, &variant->config,
-                                     &variant->info, shaders, shader_count, options,
-                                     dump_shaders);
+               radv_compile_nir_shader(tm, &binary, &variant->config,
+                                       &variant->info, shaders, shader_count,
+                                       options, dump_shaders);
        }
 
        LLVMDisposeTargetMachine(tm);
@@ -656,13 +643,15 @@ generate_shader_stats(struct radv_device *device,
                                   "VGPRS: %d\n"
                                   "Spilled SGPRs: %d\n"
                                   "Spilled VGPRs: %d\n"
+                                  "PrivMem VGPRS: %d\n"
                                   "Code Size: %d bytes\n"
                                   "LDS: %d blocks\n"
                                   "Scratch: %d bytes per wave\n"
                                   "Max Waves: %d\n"
                                   "********************\n\n\n",
                                   conf->num_sgprs, conf->num_vgprs,
-                                  conf->spilled_sgprs, conf->spilled_vgprs, variant->code_size,
+                                  conf->spilled_sgprs, conf->spilled_vgprs,
+                                  variant->info.private_mem_vgprs, variant->code_size,
                                   conf->lds_size, conf->scratch_bytes_per_wave,
                                   max_simd_waves);
 }