.vertex_id_zero_based = true,
.lower_scmp = true,
.lower_flrp32 = true,
+ .lower_flrp64 = true,
+ .lower_device_index_to_zero = true,
.lower_fsat = true,
.lower_fdiv = true,
.lower_sub = true,
.lower_extract_byte = true,
.lower_extract_word = true,
.lower_ffma = true,
+ .lower_fpow = true,
+ .vs_inputs_dual_locations = true,
.max_unroll_iterations = 32
};
NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
}
} while (progress);
+
+ NIR_PASS(progress, shader, nir_opt_shrink_load);
}
nir_shader *
}
const struct spirv_to_nir_options spirv_options = {
.caps = {
+ .device_group = true,
.draw_parameters = true,
.float64 = true,
.image_read_without_format = true,
.tessellation = true,
.int64 = true,
.multiview = true,
+ .subgroup_basic = true,
.variable_pointers = true,
},
+ .exts = {
+ .AMD_gcn_shader = true,
+ },
};
entry_point = spirv_to_nir(spirv, module->size / 4,
spec_entries, num_spec_entries,
nir_shader_gather_info(nir, entry_point->impl);
- /* While it would be nice not to have this flag, we are constrained
- * by the reality that LLVM 5.0 doesn't have working VGPR indexing
- * on GFX9.
- */
- bool llvm_has_working_vgpr_indexing =
- device->physical_device->rad_info.chip_class <= VI;
-
- /* TODO: Indirect indexing of GS inputs is unimplemented.
- *
- * TCS and TES load inputs directly from LDS or offchip memory, so
- * indirect indexing is trivial.
- */
- nir_variable_mode indirect_mask = 0;
- if (nir->info.stage == MESA_SHADER_GEOMETRY ||
- (nir->info.stage != MESA_SHADER_TESS_CTRL &&
- nir->info.stage != MESA_SHADER_TESS_EVAL &&
- !llvm_has_working_vgpr_indexing)) {
- indirect_mask |= nir_var_shader_in;
- }
- if (!llvm_has_working_vgpr_indexing &&
- nir->info.stage != MESA_SHADER_TESS_CTRL)
- indirect_mask |= nir_var_shader_out;
-
- /* TODO: We shouldn't need to do this, however LLVM isn't currently
- * smart enough to handle indirects without causing excess spilling
- * causing the gpu to hang.
- *
- * See the following thread for more details of the problem:
- * https://lists.freedesktop.org/archives/mesa-dev/2017-July/162106.html
- */
- indirect_mask |= nir_var_local;
-
- nir_lower_indirect_derefs(nir, indirect_mask);
-
static const nir_lower_tex_options tex_options = {
.lower_txp = ~0,
};
nir_lower_var_copies(nir);
nir_lower_global_vars_to_local(nir);
nir_remove_dead_variables(nir, nir_var_local);
+ ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
+ nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
+ .subgroup_size = 64,
+ .ballot_bit_size = 64,
+ .lower_to_scalar = 1,
+ .lower_subgroup_masks = 1,
+ .lower_shuffle = 1,
+ .lower_quad = 1,
+ });
+
radv_optimize_nir(nir);
return nir;
slab->size = 256 * 1024;
slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
- RADEON_DOMAIN_VRAM, RADEON_FLAG_NO_INTERPROCESS_SHARING);
+ RADEON_DOMAIN_VRAM,
+ RADEON_FLAG_NO_INTERPROCESS_SHARING |
+ device->physical_device->cpdma_prefetch_writes_memory ?
+ 0 : RADEON_FLAG_READ_ONLY);
slab->ptr = (char*)device->ws->buffer_map(slab->bo);
list_inithead(&slab->shaders);
case MESA_SHADER_FRAGMENT:
break;
case MESA_SHADER_COMPUTE: {
- struct ac_shader_info *info = &variant->info.info;
+ struct radv_shader_info *info = &variant->info.info;
variant->rsrc2 |=
- S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
- S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
+ S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
+ S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
+ S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
+ S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
+ info->cs.uses_thread_id[1] ? 1 : 0) |
S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
S_00B84C_LDS_SIZE(variant->config.lds_size);
break;
if (device->physical_device->rad_info.chip_class >= GFX9 &&
stage == MESA_SHADER_GEOMETRY) {
- /* TODO: Figure out how many we actually need. */
- variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(3);
- variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(3) |
- S_00B22C_OC_LDS_EN(1);
+ struct radv_shader_info *info = &variant->info.info;
+ unsigned es_type = variant->info.gs.es_type;
+ unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
+
+ if (es_type == MESA_SHADER_VERTEX) {
+ es_vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
+ } else if (es_type == MESA_SHADER_TESS_EVAL) {
+ es_vgpr_comp_cnt = 3;
+ } else {
+ unreachable("invalid shader ES type");
+ }
+
+ /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
+ * VGPR[0:4] are always loaded.
+ */
+ if (info->uses_invocation_id)
+ gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
+ else if (info->uses_prim_id)
+ gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
+ else if (variant->info.gs.vertices_in >= 3)
+ gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
+ else
+ gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
+
+ variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
+ variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
+ S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
} else if (device->physical_device->rad_info.chip_class >= GFX9 &&
stage == MESA_SHADER_TESS_CTRL)
variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
options->family = chip_family;
options->chip_class = device->physical_device->rad_info.chip_class;
+ options->dump_preoptir = radv_can_dump_shader(device, module) &&
+ device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
if (options->supports_spill)
tm_options |= AC_TM_SUPPORTS_SPILL;
if (gs_copy_shader) {
assert(shader_count == 1);
- ac_create_gs_copy_shader(tm, *shaders, &binary, &variant->config,
- &variant->info, options, dump_shaders);
+ radv_compile_gs_copy_shader(tm, *shaders, &binary,
+ &variant->config, &variant->info,
+ options, dump_shaders);
} else {
- ac_compile_nir_shader(tm, &binary, &variant->config,
- &variant->info, shaders, shader_count, options,
- dump_shaders);
+ radv_compile_nir_shader(tm, &binary, &variant->config,
+ &variant->info, shaders, shader_count,
+ options, dump_shaders);
}
LLVMDisposeTargetMachine(tm);
"VGPRS: %d\n"
"Spilled SGPRs: %d\n"
"Spilled VGPRs: %d\n"
+ "PrivMem VGPRS: %d\n"
"Code Size: %d bytes\n"
"LDS: %d blocks\n"
"Scratch: %d bytes per wave\n"
"Max Waves: %d\n"
"********************\n\n\n",
conf->num_sgprs, conf->num_vgprs,
- conf->spilled_sgprs, conf->spilled_vgprs, variant->code_size,
+ conf->spilled_sgprs, conf->spilled_vgprs,
+ variant->info.private_mem_vgprs, variant->code_size,
conf->lds_size, conf->scratch_bytes_per_wave,
max_simd_waves);
}
projects / mesa.git / blobdiff