radv: align the LDS size in calculate_tess_lds_size()

[mesa.git] / src / amd / vulkan / radv_shader.h

diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 21dd5188e1a862429acbc6dbae8a99b38d1f0f31..08d7fb9aff27d20bfb7db8201dbbc0d1f8d192ca 100644 (file)
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -331,7 +331,7 @@ struct radv_shader_info {
                uint64_t tes_patch_inputs_read;
                unsigned tcs_vertices_out;
                uint32_t num_patches;
-               uint32_t lds_size;
+               uint32_t num_lds_blocks;
                uint8_t num_linked_inputs;
                uint8_t num_linked_outputs;
                uint8_t num_linked_patch_outputs;
@@ -533,7 +533,8 @@ shader_io_get_unique_index(gl_varying_slot slot)
 }
 
 static inline unsigned
-calculate_tess_lds_size(unsigned tcs_num_input_vertices,
+calculate_tess_lds_size(enum chip_class chip_class,
+                       unsigned tcs_num_input_vertices,
                        unsigned tcs_num_output_vertices,
                        unsigned tcs_num_inputs,
                        unsigned tcs_num_patches,
@@ -550,7 +551,17 @@ calculate_tess_lds_size(unsigned tcs_num_input_vertices,
 
        unsigned output_patch0_offset = input_patch_size * tcs_num_patches;
 
-       return output_patch0_offset + output_patch_size * tcs_num_patches;
+       unsigned lds_size = output_patch0_offset + output_patch_size * tcs_num_patches;
+
+       if (chip_class >= GFX7) {
+               assert(lds_size <= 65536);
+               lds_size = align(lds_size, 512) / 512;
+       } else {
+               assert(lds_size <= 32768);
+               lds_size = align(lds_size, 256) / 256;
+       }
+
+       return lds_size;
 }
 
 static inline unsigned