radv: store vertex attribute formats as pipeline keys

[mesa.git] / src / amd / vulkan / radv_shader.h

diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 897e2fc5e19b3a9e066038da652e0252f79449b9..0dc965b75f52f18e00f426ea61935365ea133706 100644 (file)
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -65,6 +65,7 @@ enum {
 struct radv_vs_variant_key {
        uint32_t instance_rate_inputs;
        uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
+       uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
 
        /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
         * so we may need to fix it up. */
@@ -129,9 +130,11 @@ struct radv_nir_compiler_options {
 enum radv_ud_index {
        AC_UD_SCRATCH_RING_OFFSETS = 0,
        AC_UD_PUSH_CONSTANTS = 1,
-       AC_UD_INDIRECT_DESCRIPTOR_SETS = 2,
-       AC_UD_VIEW_INDEX = 3,
-       AC_UD_SHADER_START = 4,
+       AC_UD_INLINE_PUSH_CONSTANTS = 2,
+       AC_UD_INDIRECT_DESCRIPTOR_SETS = 3,
+       AC_UD_VIEW_INDEX = 4,
+       AC_UD_STREAMOUT_BUFFERS = 5,
+       AC_UD_SHADER_START = 6,
        AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
        AC_UD_VS_BASE_VERTEX_START_INSTANCE,
        AC_UD_VS_MAX_UD,
@@ -143,8 +146,31 @@ enum radv_ud_index {
        AC_UD_TES_MAX_UD,
        AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
 };
+
+struct radv_stream_output {
+       uint8_t location;
+       uint8_t buffer;
+       uint16_t offset;
+       uint8_t component_mask;
+       uint8_t stream;
+};
+
+struct radv_streamout_info {
+       uint16_t num_outputs;
+       struct radv_stream_output outputs[MAX_SO_OUTPUTS];
+       uint16_t strides[MAX_SO_BUFFERS];
+       uint32_t enabled_stream_buffers_mask;
+};
+
 struct radv_shader_info {
        bool loads_push_constants;
+       bool loads_dynamic_offsets;
+       uint8_t min_push_constant_used;
+       uint8_t max_push_constant_used;
+       bool has_only_32bit_push_constants;
+       bool has_indirect_push_constants;
+       uint8_t num_inline_push_consts;
+       uint8_t base_inline_push_consts;
        uint32_t desc_set_used_mask;
        bool needs_multiview_view_index;
        bool uses_invocation_id;
@@ -159,6 +185,9 @@ struct radv_shader_info {
        } vs;
        struct {
                uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
+               uint8_t num_stream_output_components[4];
+               uint8_t output_streams[VARYING_SLOT_VAR31 + 1];
+               uint8_t max_stream;
        } gs;
        struct {
                uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
@@ -186,13 +215,13 @@ struct radv_shader_info {
                uint64_t outputs_written;
                uint64_t patch_outputs_written;
        } tcs;
+
+       struct radv_streamout_info so;
 };
 
 struct radv_userdata_info {
        int8_t sgpr_idx;
        uint8_t num_sgprs;
-       bool indirect;
-       uint32_t indirect_offset;
 };
 
 struct radv_userdata_locations {
@@ -299,7 +328,8 @@ struct radv_shader_slab {
 };
 
 void
-radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively);
+radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
+                 bool allow_copies);
 
 nir_shader *
 radv_shader_compile_to_nir(struct radv_device *device,
@@ -386,10 +416,4 @@ static inline unsigned shader_io_get_unique_index(gl_varying_slot slot)
        unreachable("illegal slot in get unique index\n");
 }
 
-static inline uint32_t
-radv_get_num_physical_sgprs(struct radv_physical_device *physical_device)
-{
-       return physical_device->rad_info.chip_class >= VI ? 800 : 512;
-}
-
 #endif