uint32_t as_es:1;
uint32_t as_ls:1;
uint32_t as_ngg:1;
+ uint32_t as_ngg_passthrough:1;
uint32_t export_prim_id:1;
uint32_t export_layer_id:1;
uint32_t export_clip_dists:1;
/* For some formats the channels have to be shuffled. */
uint32_t post_shuffle;
+
+ /* Output primitive type. */
+ uint8_t outprim;
};
struct radv_tes_variant_key {
uint32_t is_int10;
};
+struct radv_cs_variant_key {
+ uint8_t subgroup_size;
+};
+
struct radv_shader_variant_key {
union {
struct radv_vs_variant_key vs;
struct radv_fs_variant_key fs;
struct radv_tes_variant_key tes;
struct radv_tcs_variant_key tcs;
+ struct radv_cs_variant_key cs;
/* A common prefix of the vs and tes keys. */
struct radv_vs_out_key vs_common_out;
struct radv_nir_compiler_options {
struct radv_pipeline_layout *layout;
struct radv_shader_variant_key key;
- bool unsafe_math;
- bool supports_spill;
+ bool explicit_scratch_args;
bool clamp_shadow_reference;
bool robust_buffer_access;
bool dump_shader;
bool dump_preoptir;
- bool record_llvm_ir;
+ bool record_ir;
bool check_ir;
bool has_ls_vgpr_init_bug;
+ bool use_ngg_streamout;
enum radeon_family family;
enum chip_class chip_class;
uint32_t tess_offchip_block_dw_size;
uint32_t address32_hi;
- uint8_t wave_size;
};
enum radv_ud_index {
AC_UD_INDIRECT_DESCRIPTOR_SETS = 3,
AC_UD_VIEW_INDEX = 4,
AC_UD_STREAMOUT_BUFFERS = 5,
- AC_UD_SHADER_START = 6,
+ AC_UD_NGG_GS_STATE = 6,
+ AC_UD_SHADER_START = 7,
AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
AC_UD_VS_BASE_VERTEX_START_INSTANCE,
AC_UD_VS_MAX_UD,
uint32_t max_out_verts;
uint32_t prim_amp_factor;
uint32_t vgt_esgs_ring_itemsize;
+ uint32_t esgs_ring_size;
bool max_vert_out_per_gs_instance;
};
unsigned private_mem_vgprs;
bool need_indirect_descriptor_sets;
bool is_ngg;
+ bool is_ngg_passthrough;
struct {
uint64_t ls_outputs_written;
uint8_t input_usage_mask[VERT_ATTRIB_MAX];
uint8_t num_stream_output_components[4];
uint8_t output_streams[VARYING_SLOT_VAR31 + 1];
uint8_t max_stream;
+ bool writes_memory;
unsigned gsvs_vertex_size;
unsigned max_gsvs_emit_size;
unsigned vertices_in;
uint8_t num_input_clips_culls;
uint32_t input_mask;
uint32_t flat_shaded_mask;
+ uint32_t explicit_shaded_mask;
uint32_t float16_shaded_mask;
uint32_t num_interp;
bool can_discard;
struct gfx9_gs_info gs_ring_info;
struct gfx10_ngg_info ngg_info;
+
+ unsigned float_controls_mode;
};
enum radv_shader_binary_type {
struct radv_shader_binary base;
struct ac_shader_config config;
unsigned code_size;
- unsigned llvm_ir_size;
+ unsigned exec_size;
+ unsigned ir_size;
unsigned disasm_size;
- /* data has size of code_size + llvm_ir_size + disasm_size + 2, where
+ /* data has size of code_size + ir_size + disasm_size + 2, where
* the +2 is for 0 of the ir strings. */
uint8_t data[0];
};
struct radv_shader_info info;
/* debug only */
- uint32_t *spirv;
+ char *spirv;
uint32_t spirv_size;
char *nir_string;
char *disasm_string;
- char *llvm_ir_string;
+ char *ir_string;
struct list_head slab_list;
};
gl_shader_stage stage,
const VkSpecializationInfo *spec_info,
const VkPipelineCreateFlags flags,
- const struct radv_pipeline_layout *layout);
+ const struct radv_pipeline_layout *layout,
+ unsigned subgroup_size);
void *
radv_alloc_shader_memory(struct radv_device *device,
void
radv_destroy_shader_slabs(struct radv_device *device);
+void
+radv_create_shaders(struct radv_pipeline *pipeline,
+ struct radv_device *device,
+ struct radv_pipeline_cache *cache,
+ const struct radv_pipeline_key *key,
+ const VkPipelineShaderStageCreateInfo **pStages,
+ const VkPipelineCreateFlags flags,
+ VkPipelineCreationFeedbackEXT *pipeline_feedback,
+ VkPipelineCreationFeedbackEXT **stage_feedbacks);
+
struct radv_shader_variant *
radv_shader_variant_create(struct radv_device *device,
const struct radv_shader_binary *binary,
radv_can_dump_shader_stats(struct radv_device *device,
struct radv_shader_module *module);
-unsigned
-shader_io_get_unique_index(gl_varying_slot slot);
+static inline unsigned
+shader_io_get_unique_index(gl_varying_slot slot)
+{
+ /* handle patch indices separate */
+ if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
+ return 0;
+ if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
+ return 1;
+ if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
+ return 2 + (slot - VARYING_SLOT_PATCH0);
+ if (slot == VARYING_SLOT_POS)
+ return 0;
+ if (slot == VARYING_SLOT_PSIZ)
+ return 1;
+ if (slot == VARYING_SLOT_CLIP_DIST0)
+ return 2;
+ if (slot == VARYING_SLOT_CLIP_DIST1)
+ return 3;
+ /* 3 is reserved for clip dist as well */
+ if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
+ return 4 + (slot - VARYING_SLOT_VAR0);
+ unreachable("illegal slot in get unique index\n");
+}
+
+static inline unsigned
+calculate_tess_lds_size(unsigned tcs_num_input_vertices,
+ unsigned tcs_num_output_vertices,
+ unsigned tcs_num_inputs,
+ unsigned tcs_num_patches,
+ unsigned tcs_outputs_written,
+ unsigned tcs_per_patch_outputs_written)
+{
+ unsigned num_tcs_outputs = util_last_bit64(tcs_outputs_written);
+ unsigned num_tcs_patch_outputs = util_last_bit64(tcs_per_patch_outputs_written);
+
+ unsigned input_vertex_size = tcs_num_inputs * 16;
+ unsigned output_vertex_size = num_tcs_outputs * 16;
+
+ unsigned input_patch_size = tcs_num_input_vertices * input_vertex_size;
+
+ unsigned pervertex_output_patch_size = tcs_num_output_vertices * output_vertex_size;
+ unsigned output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
+
+ unsigned output_patch0_offset = input_patch_size * tcs_num_patches;
+
+ return output_patch0_offset + output_patch_size * tcs_num_patches;
+}
+
+static inline unsigned
+get_tcs_num_patches(unsigned tcs_num_input_vertices,
+ unsigned tcs_num_output_vertices,
+ unsigned tcs_num_inputs,
+ unsigned tcs_outputs_written,
+ unsigned tcs_per_patch_outputs_written,
+ unsigned tess_offchip_block_dw_size,
+ enum chip_class chip_class,
+ enum radeon_family family)
+{
+ uint32_t input_vertex_size = tcs_num_inputs * 16;
+ uint32_t input_patch_size = tcs_num_input_vertices * input_vertex_size;
+ uint32_t num_tcs_outputs = util_last_bit64(tcs_outputs_written);
+ uint32_t num_tcs_patch_outputs = util_last_bit64(tcs_per_patch_outputs_written);
+ uint32_t output_vertex_size = num_tcs_outputs * 16;
+ uint32_t pervertex_output_patch_size = tcs_num_output_vertices * output_vertex_size;
+ uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
+
+ /* Ensure that we only need one wave per SIMD so we don't need to check
+ * resource usage. Also ensures that the number of tcs in and out
+ * vertices per threadgroup are at most 256.
+ */
+ unsigned num_patches = 64 / MAX2(tcs_num_input_vertices, tcs_num_output_vertices) * 4;
+ /* Make sure that the data fits in LDS. This assumes the shaders only
+ * use LDS for the inputs and outputs.
+ */
+ unsigned hardware_lds_size = 32768;
+
+ /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
+ * threadgroup, even though there is more than 32 KiB LDS.
+ *
+ * Test: dEQP-VK.tessellation.shader_input_output.barrier
+ */
+ if (chip_class >= GFX7 && family != CHIP_STONEY)
+ hardware_lds_size = 65536;
+
+ num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
+ /* Make sure the output data fits in the offchip buffer */
+ num_patches = MIN2(num_patches, (tess_offchip_block_dw_size * 4) / output_patch_size);
+ /* Not necessary for correctness, but improves performance. The
+ * specific value is taken from the proprietary driver.
+ */
+ num_patches = MIN2(num_patches, 40);
+
+ /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
+ if (chip_class == GFX6) {
+ unsigned one_wave = 64 / MAX2(tcs_num_input_vertices, tcs_num_output_vertices);
+ num_patches = MIN2(num_patches, one_wave);
+ }
+ return num_patches;
+}
void
radv_lower_fs_io(nir_shader *nir);
projects / mesa.git / blobdiff