mesa: include mtypes.h less

[mesa.git] / src / amd / vulkan / radv_shader.h

diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 4b83095c9728da8dee13e725b39ecf4ef8506c38..6588b7877249096a63aede4b565c3c3c935a1e8e 100644 (file)
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -46,6 +46,8 @@
 // Match MAX_SETS from radv_descriptor_set.h
 #define RADV_UD_MAX_SETS MAX_SETS
 
+#define RADV_NUM_PHYSICAL_VGPRS 256
+
 struct radv_shader_module {
        struct nir_shader *nir;
        unsigned char sha1[20];
@@ -55,14 +57,17 @@ struct radv_shader_module {
 
 struct radv_vs_variant_key {
        uint32_t instance_rate_inputs;
+       uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
        uint32_t as_es:1;
        uint32_t as_ls:1;
        uint32_t export_prim_id:1;
+       uint32_t export_layer_id:1;
 };
 
 struct radv_tes_variant_key {
        uint32_t as_es:1;
        uint32_t export_prim_id:1;
+       uint32_t export_layer_id:1;
        uint8_t num_patches;
        uint8_t tcs_num_outputs;
 };
@@ -121,7 +126,6 @@ enum radv_ud_index {
        AC_UD_PS_MAX_UD,
        AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
        AC_UD_CS_MAX_UD,
-       AC_UD_GS_VS_RING_STRIDE_ENTRIES = AC_UD_VS_MAX_UD,
        AC_UD_GS_MAX_UD,
        AC_UD_TCS_MAX_UD,
        AC_UD_TES_MAX_UD,
@@ -211,7 +215,6 @@ struct radv_shader_variant_info {
                        unsigned vgpr_comp_cnt;
                        bool as_es;
                        bool as_ls;
-                       uint64_t outputs_written;
                } vs;
                struct {
                        unsigned num_interp;
@@ -234,11 +237,8 @@ struct radv_shader_variant_info {
                } gs;
                struct {
                        unsigned tcs_vertices_out;
-                       /* Which outputs are actually written */
-                       uint64_t outputs_written;
-                       /* Which patch outputs are actually written */
-                       uint32_t patch_outputs_written;
                        uint32_t num_patches;
+                       uint32_t lds_size;
                } tcs;
                struct {
                        struct radv_vs_output_info outinfo;
@@ -365,4 +365,10 @@ static inline unsigned shader_io_get_unique_index(gl_varying_slot slot)
        unreachable("illegal slot in get unique index\n");
 }
 
+static inline uint32_t
+radv_get_num_physical_sgprs(struct radv_physical_device *physical_device)
+{
+       return physical_device->rad_info.chip_class >= VI ? 800 : 512;
+}
+
 #endif