// Match MAX_SETS from radv_descriptor_set.h
#define RADV_UD_MAX_SETS MAX_SETS
+#define RADV_NUM_PHYSICAL_VGPRS 256
+
struct radv_shader_module {
struct nir_shader *nir;
unsigned char sha1[20];
char data[0];
};
+enum {
+ RADV_ALPHA_ADJUST_NONE = 0,
+ RADV_ALPHA_ADJUST_SNORM = 1,
+ RADV_ALPHA_ADJUST_SINT = 2,
+ RADV_ALPHA_ADJUST_SSCALED = 3,
+};
+
struct radv_vs_variant_key {
uint32_t instance_rate_inputs;
+ uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
+
+ /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
+ * so we may need to fix it up. */
+ uint64_t alpha_adjust;
+
uint32_t as_es:1;
uint32_t as_ls:1;
uint32_t export_prim_id:1;
+ uint32_t export_layer_id:1;
};
struct radv_tes_variant_key {
uint32_t as_es:1;
uint32_t export_prim_id:1;
+ uint32_t export_layer_id:1;
uint8_t num_patches;
uint8_t tcs_num_outputs;
};
struct radv_fs_variant_key {
uint32_t col_format;
uint8_t log2_ps_iter_samples;
- uint8_t log2_num_samples;
+ uint8_t num_samples;
uint32_t is_int8;
uint32_t is_int10;
- uint32_t multisample : 1;
};
struct radv_shader_variant_key {
bool dump_shader;
bool dump_preoptir;
bool record_llvm_ir;
+ bool check_ir;
enum radeon_family family;
enum chip_class chip_class;
uint32_t tess_offchip_block_dw_size;
+ uint32_t address32_hi;
};
enum radv_ud_index {
AC_UD_PUSH_CONSTANTS = 1,
AC_UD_INDIRECT_DESCRIPTOR_SETS = 2,
AC_UD_VIEW_INDEX = 3,
- AC_UD_SHADER_START = 4,
+ AC_UD_STREAMOUT_BUFFERS = 4,
+ AC_UD_SHADER_START = 5,
AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
AC_UD_VS_BASE_VERTEX_START_INSTANCE,
AC_UD_VS_MAX_UD,
- AC_UD_PS_SAMPLE_POS_OFFSET = AC_UD_SHADER_START,
AC_UD_PS_MAX_UD,
AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
AC_UD_CS_MAX_UD,
- AC_UD_GS_VS_RING_STRIDE_ENTRIES = AC_UD_VS_MAX_UD,
AC_UD_GS_MAX_UD,
AC_UD_TCS_MAX_UD,
AC_UD_TES_MAX_UD,
AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
};
+
+struct radv_stream_output {
+ uint8_t location;
+ uint8_t buffer;
+ uint16_t offset;
+ uint8_t component_mask;
+ uint8_t stream;
+};
+
+struct radv_streamout_info {
+ uint16_t num_outputs;
+ struct radv_stream_output outputs[MAX_SO_OUTPUTS];
+ uint16_t strides[MAX_SO_BUFFERS];
+ uint32_t enabled_stream_buffers_mask;
+};
+
struct radv_shader_info {
bool loads_push_constants;
+ uint8_t min_push_constant_used;
+ uint8_t max_push_constant_used;
+ bool has_only_32bit_push_constants;
+ bool has_indirect_push_constants;
uint32_t desc_set_used_mask;
bool needs_multiview_view_index;
bool uses_invocation_id;
bool needs_draw_id;
bool needs_instance_id;
} vs;
+ struct {
+ uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
+ uint8_t num_stream_output_components[4];
+ uint8_t output_streams[VARYING_SLOT_VAR31 + 1];
+ uint8_t max_stream;
+ } gs;
struct {
uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
} tes;
bool has_pcoord;
bool prim_id_input;
bool layer_input;
+ uint8_t num_input_clips_culls;
} ps;
struct {
bool uses_grid_size;
uint64_t outputs_written;
uint64_t patch_outputs_written;
} tcs;
+
+ struct radv_streamout_info so;
};
struct radv_userdata_info {
int8_t sgpr_idx;
uint8_t num_sgprs;
- bool indirect;
- uint32_t indirect_offset;
};
struct radv_userdata_locations {
struct radv_userdata_info descriptor_sets[RADV_UD_MAX_SETS];
struct radv_userdata_info shader_data[AC_UD_MAX_UD];
+ uint32_t descriptor_sets_enabled;
};
struct radv_vs_output_info {
};
void
-radv_optimize_nir(struct nir_shader *shader);
+radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
+ bool allow_copies);
nir_shader *
radv_shader_compile_to_nir(struct radv_device *device,
struct radv_shader_module *module,
const char *entrypoint_name,
gl_shader_stage stage,
- const VkSpecializationInfo *spec_info);
+ const VkSpecializationInfo *spec_info,
+ const VkPipelineCreateFlags flags);
void *
radv_alloc_shader_memory(struct radv_device *device,
static inline bool
radv_can_dump_shader(struct radv_device *device,
- struct radv_shader_module *module)
+ struct radv_shader_module *module,
+ bool is_gs_copy_shader)
{
+ if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
+ return false;
+
/* Only dump non-meta shaders, useful for debugging purposes. */
- return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS &&
- module && !module->nir;
+ return (module && !module->nir) || is_gs_copy_shader;
}
static inline bool