bool unsafe_math;
bool supports_spill;
bool clamp_shadow_reference;
+ bool dump_shader;
bool dump_preoptir;
+ bool record_llvm_ir;
enum radeon_family family;
enum chip_class chip_class;
};
bool uses_invocation_id;
bool uses_prim_id;
struct {
+ uint64_t ls_outputs_written;
uint8_t input_usage_mask[VERT_ATTRIB_MAX];
uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
bool has_vertex_buffers; /* needs vertex buffers and base/start */
bool uses_thread_id[3];
bool uses_local_invocation_idx;
} cs;
+ struct {
+ uint64_t outputs_written;
+ uint64_t patch_outputs_written;
+ } tcs;
};
struct radv_userdata_info {
uint32_t spirv_size;
struct nir_shader *nir;
char *disasm_string;
+ char *llvm_ir_string;
struct list_head slab_list;
};
module && !module->nir;
}
+static inline unsigned shader_io_get_unique_index(gl_varying_slot slot)
+{
+ /* handle patch indices separate */
+ if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
+ return 0;
+ if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
+ return 1;
+ if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
+ return 2 + (slot - VARYING_SLOT_PATCH0);
+ if (slot == VARYING_SLOT_POS)
+ return 0;
+ if (slot == VARYING_SLOT_PSIZ)
+ return 1;
+ if (slot == VARYING_SLOT_CLIP_DIST0)
+ return 2;
+ /* 3 is reserved for clip dist as well */
+ if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
+ return 4 + (slot - VARYING_SLOT_VAR0);
+ unreachable("illegal slot in get unique index\n");
+}
+
#endif