radv: gather info about PS inputs in the shader info pass
[mesa.git] / src / amd / vulkan / radv_shader.h
index 0ab7db20181498ae79f5bf547a7a3fd0fe283018..b8770b8c999db01a403290a01056009cd8d3d832 100644 (file)
@@ -120,17 +120,17 @@ struct radv_nir_compiler_options {
        bool unsafe_math;
        bool supports_spill;
        bool clamp_shadow_reference;
+       bool robust_buffer_access;
        bool dump_shader;
        bool dump_preoptir;
        bool record_llvm_ir;
        bool check_ir;
+       bool has_ls_vgpr_init_bug;
        enum radeon_family family;
        enum chip_class chip_class;
        uint32_t tess_offchip_block_dw_size;
        uint32_t address32_hi;
-       uint8_t cs_wave_size;
-       uint8_t ps_wave_size;
-       uint8_t ge_wave_size;
+       uint8_t wave_size;
 };
 
 enum radv_ud_index {
@@ -181,6 +181,7 @@ struct radv_shader_info {
        bool needs_multiview_view_index;
        bool uses_invocation_id;
        bool uses_prim_id;
+       uint8_t wave_size;
        struct {
                uint64_t ls_outputs_written;
                uint8_t input_usage_mask[VERT_ATTRIB_MAX];
@@ -209,6 +210,10 @@ struct radv_shader_info {
                bool prim_id_input;
                bool layer_input;
                uint8_t num_input_clips_culls;
+               uint32_t input_mask;
+               uint32_t flat_shaded_mask;
+               uint32_t float16_shaded_mask;
+               uint32_t num_interp;
        } ps;
        struct {
                bool uses_grid_size;
@@ -269,10 +274,6 @@ struct radv_shader_variant_info {
                        bool export_prim_id;
                } vs;
                struct {
-                       unsigned num_interp;
-                       uint32_t input_mask;
-                       uint32_t flat_shaded_mask;
-                       uint32_t float16_shaded_mask;
                        bool can_discard;
                        bool early_fragment_test;
                        bool post_depth_coverage;
@@ -354,7 +355,7 @@ struct radv_shader_variant {
        /* debug only */
        uint32_t *spirv;
        uint32_t spirv_size;
-       struct nir_shader *nir;
+       char *nir_string;
        char *disasm_string;
        char *llvm_ir_string;
 
@@ -394,7 +395,8 @@ radv_destroy_shader_slabs(struct radv_device *device);
 
 struct radv_shader_variant *
 radv_shader_variant_create(struct radv_device *device,
-                          const struct radv_shader_binary *binary);
+                          const struct radv_shader_binary *binary,
+                          bool keep_shader_info);
 struct radv_shader_variant *
 radv_shader_variant_compile(struct radv_device *device,
                            struct radv_shader_module *module,
@@ -402,17 +404,29 @@ radv_shader_variant_compile(struct radv_device *device,
                            int shader_count,
                            struct radv_pipeline_layout *layout,
                            const struct radv_shader_variant_key *key,
+                           bool keep_shader_info,
                            struct radv_shader_binary **binary_out);
 
 struct radv_shader_variant *
 radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *nir,
                           struct radv_shader_binary **binary_out,
-                          bool multiview);
+                          bool multiview,  bool keep_shader_info);
 
 void
 radv_shader_variant_destroy(struct radv_device *device,
                            struct radv_shader_variant *variant);
 
+
+unsigned
+radv_get_max_waves(struct radv_device *device,
+                   struct radv_shader_variant *variant,
+                   gl_shader_stage stage);
+
+unsigned
+radv_get_max_workgroup_size(enum chip_class chip_class,
+                            gl_shader_stage stage,
+                            const unsigned *sizes);
+
 const char *
 radv_get_shader_name(struct radv_shader_variant_info *info,
                     gl_shader_stage stage);