struct radv_vs_variant_key {
uint32_t instance_rate_inputs;
uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
+ uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
+ uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
+ uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
+ uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
/* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
* so we may need to fix it up. */
uint64_t alpha_adjust;
+ /* For some formats the channels have to be shuffled. */
+ uint32_t post_shuffle;
+
uint32_t as_es:1;
uint32_t as_ls:1;
uint32_t export_prim_id:1;
unsigned num_interp;
uint32_t input_mask;
uint32_t flat_shaded_mask;
+ uint32_t float16_shaded_mask;
bool can_discard;
bool early_fragment_test;
} fs;
void
radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
bool allow_copies);
+bool
+radv_nir_lower_ycbcr_textures(nir_shader *shader,
+ const struct radv_pipeline_layout *layout);
nir_shader *
radv_shader_compile_to_nir(struct radv_device *device,
const char *entrypoint_name,
gl_shader_stage stage,
const VkSpecializationInfo *spec_info,
- const VkPipelineCreateFlags flags);
+ const VkPipelineCreateFlags flags,
+ const struct radv_pipeline_layout *layout);
void *
radv_alloc_shader_memory(struct radv_device *device,
return 1;
if (slot == VARYING_SLOT_CLIP_DIST0)
return 2;
+ if (slot == VARYING_SLOT_CLIP_DIST1)
+ return 3;
/* 3 is reserved for clip dist as well */
if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
return 4 + (slot - VARYING_SLOT_VAR0);