char data[0];
};
+enum {
+ RADV_ALPHA_ADJUST_NONE = 0,
+ RADV_ALPHA_ADJUST_SNORM = 1,
+ RADV_ALPHA_ADJUST_SINT = 2,
+ RADV_ALPHA_ADJUST_SSCALED = 3,
+};
+
struct radv_vs_variant_key {
uint32_t instance_rate_inputs;
uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
+
+ /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
+ * so we may need to fix it up. */
+ uint64_t alpha_adjust;
+
uint32_t as_es:1;
uint32_t as_ls:1;
uint32_t export_prim_id:1;
struct radv_fs_variant_key {
uint32_t col_format;
uint8_t log2_ps_iter_samples;
- uint8_t log2_num_samples;
+ uint8_t num_samples;
uint32_t is_int8;
uint32_t is_int10;
- uint32_t multisample : 1;
};
struct radv_shader_variant_key {
bool dump_shader;
bool dump_preoptir;
bool record_llvm_ir;
+ bool check_ir;
enum radeon_family family;
enum chip_class chip_class;
uint32_t tess_offchip_block_dw_size;
+ uint32_t address32_hi;
};
enum radv_ud_index {
AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
AC_UD_VS_BASE_VERTEX_START_INSTANCE,
AC_UD_VS_MAX_UD,
- AC_UD_PS_SAMPLE_POS_OFFSET = AC_UD_SHADER_START,
AC_UD_PS_MAX_UD,
AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
AC_UD_CS_MAX_UD,
bool needs_draw_id;
bool needs_instance_id;
} vs;
+ struct {
+ uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
+ } gs;
struct {
uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
} tes;