radv: change the returned error in radv_signal_fence()

[mesa.git] / src / amd / vulkan / radv_shader.h

diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 4b83095c9728da8dee13e725b39ecf4ef8506c38..ce7682e8bf7e3af7d9b7a856c930b080a38c723a 100644 (file)
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -46,6 +46,8 @@
 // Match MAX_SETS from radv_descriptor_set.h
 #define RADV_UD_MAX_SETS MAX_SETS
 
+#define RADV_NUM_PHYSICAL_VGPRS 256
+
 struct radv_shader_module {
        struct nir_shader *nir;
        unsigned char sha1[20];
@@ -53,16 +55,31 @@ struct radv_shader_module {
        char data[0];
 };
 
+enum {
+       RADV_ALPHA_ADJUST_NONE = 0,
+       RADV_ALPHA_ADJUST_SNORM = 1,
+       RADV_ALPHA_ADJUST_SINT = 2,
+       RADV_ALPHA_ADJUST_SSCALED = 3,
+};
+
 struct radv_vs_variant_key {
        uint32_t instance_rate_inputs;
+       uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
+
+       /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
+        * so we may need to fix it up. */
+       uint64_t alpha_adjust;
+
        uint32_t as_es:1;
        uint32_t as_ls:1;
        uint32_t export_prim_id:1;
+       uint32_t export_layer_id:1;
 };
 
 struct radv_tes_variant_key {
        uint32_t as_es:1;
        uint32_t export_prim_id:1;
+       uint32_t export_layer_id:1;
        uint8_t num_patches;
        uint8_t tcs_num_outputs;
 };
@@ -78,10 +95,9 @@ struct radv_tcs_variant_key {
 struct radv_fs_variant_key {
        uint32_t col_format;
        uint8_t log2_ps_iter_samples;
-       uint8_t log2_num_samples;
+       uint8_t num_samples;
        uint32_t is_int8;
        uint32_t is_int10;
-       uint32_t multisample : 1;
 };
 
 struct radv_shader_variant_key {
@@ -103,9 +119,11 @@ struct radv_nir_compiler_options {
        bool dump_shader;
        bool dump_preoptir;
        bool record_llvm_ir;
+       bool check_ir;
        enum radeon_family family;
        enum chip_class chip_class;
        uint32_t tess_offchip_block_dw_size;
+       uint32_t address32_hi;
 };
 
 enum radv_ud_index {
@@ -117,11 +135,9 @@ enum radv_ud_index {
        AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
        AC_UD_VS_BASE_VERTEX_START_INSTANCE,
        AC_UD_VS_MAX_UD,
-       AC_UD_PS_SAMPLE_POS_OFFSET = AC_UD_SHADER_START,
        AC_UD_PS_MAX_UD,
        AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
        AC_UD_CS_MAX_UD,
-       AC_UD_GS_VS_RING_STRIDE_ENTRIES = AC_UD_VS_MAX_UD,
        AC_UD_GS_MAX_UD,
        AC_UD_TCS_MAX_UD,
        AC_UD_TES_MAX_UD,
@@ -141,6 +157,9 @@ struct radv_shader_info {
                bool needs_draw_id;
                bool needs_instance_id;
        } vs;
+       struct {
+               uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
+       } gs;
        struct {
                uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
        } tes;
@@ -211,7 +230,6 @@ struct radv_shader_variant_info {
                        unsigned vgpr_comp_cnt;
                        bool as_es;
                        bool as_ls;
-                       uint64_t outputs_written;
                } vs;
                struct {
                        unsigned num_interp;
@@ -234,11 +252,8 @@ struct radv_shader_variant_info {
                } gs;
                struct {
                        unsigned tcs_vertices_out;
-                       /* Which outputs are actually written */
-                       uint64_t outputs_written;
-                       /* Which patch outputs are actually written */
-                       uint32_t patch_outputs_written;
                        uint32_t num_patches;
+                       uint32_t lds_size;
                } tcs;
                struct {
                        struct radv_vs_output_info outinfo;
@@ -282,14 +297,15 @@ struct radv_shader_slab {
 };
 
 void
-radv_optimize_nir(struct nir_shader *shader);
+radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively);
 
 nir_shader *
 radv_shader_compile_to_nir(struct radv_device *device,
                           struct radv_shader_module *module,
                           const char *entrypoint_name,
                           gl_shader_stage stage,
-                          const VkSpecializationInfo *spec_info);
+                          const VkSpecializationInfo *spec_info,
+                          const VkPipelineCreateFlags flags);
 
 void *
 radv_alloc_shader_memory(struct radv_device *device,
@@ -328,11 +344,14 @@ radv_shader_dump_stats(struct radv_device *device,
 
 static inline bool
 radv_can_dump_shader(struct radv_device *device,
-                    struct radv_shader_module *module)
+                    struct radv_shader_module *module,
+                    bool is_gs_copy_shader)
 {
+       if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
+               return false;
+
        /* Only dump non-meta shaders, useful for debugging purposes. */
-       return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS &&
-              module && !module->nir;
+       return (module && !module->nir) || is_gs_copy_shader;
 }
 
 static inline bool
@@ -365,4 +384,10 @@ static inline unsigned shader_io_get_unique_index(gl_varying_slot slot)
        unreachable("illegal slot in get unique index\n");
 }
 
+static inline uint32_t
+radv_get_num_physical_sgprs(struct radv_physical_device *physical_device)
+{
+       return physical_device->rad_info.chip_class >= VI ? 800 : 512;
+}
+
 #endif