// Match MAX_SETS from radv_descriptor_set.h
#define RADV_UD_MAX_SETS MAX_SETS
+#define RADV_NUM_PHYSICAL_VGPRS 256
+
struct radv_shader_module {
struct nir_shader *nir;
unsigned char sha1[20];
char data[0];
};
+enum {
+ RADV_ALPHA_ADJUST_NONE = 0,
+ RADV_ALPHA_ADJUST_SNORM = 1,
+ RADV_ALPHA_ADJUST_SINT = 2,
+ RADV_ALPHA_ADJUST_SSCALED = 3,
+};
+
+struct radv_vs_variant_key {
+ uint32_t instance_rate_inputs;
+ uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
+
+ /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
+ * so we may need to fix it up. */
+ uint64_t alpha_adjust;
+
+ uint32_t as_es:1;
+ uint32_t as_ls:1;
+ uint32_t export_prim_id:1;
+ uint32_t export_layer_id:1;
+};
+
+struct radv_tes_variant_key {
+ uint32_t as_es:1;
+ uint32_t export_prim_id:1;
+ uint32_t export_layer_id:1;
+ uint8_t num_patches;
+ uint8_t tcs_num_outputs;
+};
+
+struct radv_tcs_variant_key {
+ struct radv_vs_variant_key vs_key;
+ unsigned primitive_mode;
+ unsigned input_vertices;
+ unsigned num_inputs;
+ uint32_t tes_reads_tess_factors:1;
+};
+
+struct radv_fs_variant_key {
+ uint32_t col_format;
+ uint8_t log2_ps_iter_samples;
+ uint8_t log2_num_samples;
+ uint32_t is_int8;
+ uint32_t is_int10;
+};
+
+struct radv_shader_variant_key {
+ union {
+ struct radv_vs_variant_key vs;
+ struct radv_fs_variant_key fs;
+ struct radv_tes_variant_key tes;
+ struct radv_tcs_variant_key tcs;
+ };
+ bool has_multiview_view_index;
+};
+
+struct radv_nir_compiler_options {
+ struct radv_pipeline_layout *layout;
+ struct radv_shader_variant_key key;
+ bool unsafe_math;
+ bool supports_spill;
+ bool clamp_shadow_reference;
+ bool dump_shader;
+ bool dump_preoptir;
+ bool record_llvm_ir;
+ bool check_ir;
+ enum radeon_family family;
+ enum chip_class chip_class;
+ uint32_t tess_offchip_block_dw_size;
+ uint32_t address32_hi;
+};
+
+enum radv_ud_index {
+ AC_UD_SCRATCH_RING_OFFSETS = 0,
+ AC_UD_PUSH_CONSTANTS = 1,
+ AC_UD_INDIRECT_DESCRIPTOR_SETS = 2,
+ AC_UD_VIEW_INDEX = 3,
+ AC_UD_SHADER_START = 4,
+ AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
+ AC_UD_VS_BASE_VERTEX_START_INSTANCE,
+ AC_UD_VS_MAX_UD,
+ AC_UD_PS_SAMPLE_POS_OFFSET = AC_UD_SHADER_START,
+ AC_UD_PS_MAX_UD,
+ AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
+ AC_UD_CS_MAX_UD,
+ AC_UD_GS_MAX_UD,
+ AC_UD_TCS_MAX_UD,
+ AC_UD_TES_MAX_UD,
+ AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
+};
struct radv_shader_info {
bool loads_push_constants;
uint32_t desc_set_used_mask;
bool uses_invocation_id;
bool uses_prim_id;
struct {
+ uint64_t ls_outputs_written;
uint8_t input_usage_mask[VERT_ATTRIB_MAX];
uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
bool has_vertex_buffers; /* needs vertex buffers and base/start */
bool needs_draw_id;
bool needs_instance_id;
} vs;
+ struct {
+ uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
+ } gs;
struct {
uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
} tes;
bool uses_thread_id[3];
bool uses_local_invocation_idx;
} cs;
+ struct {
+ uint64_t outputs_written;
+ uint64_t patch_outputs_written;
+ } tcs;
};
struct radv_userdata_info {
unsigned vgpr_comp_cnt;
bool as_es;
bool as_ls;
- uint64_t outputs_written;
} vs;
struct {
unsigned num_interp;
} gs;
struct {
unsigned tcs_vertices_out;
- /* Which outputs are actually written */
- uint64_t outputs_written;
- /* Which patch outputs are actually written */
- uint32_t patch_outputs_written;
-
+ uint32_t num_patches;
+ uint32_t lds_size;
} tcs;
struct {
struct radv_vs_output_info outinfo;
uint32_t spirv_size;
struct nir_shader *nir;
char *disasm_string;
+ char *llvm_ir_string;
struct list_head slab_list;
};
};
void
-radv_optimize_nir(struct nir_shader *shader);
+radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively);
nir_shader *
radv_shader_compile_to_nir(struct radv_device *device,
struct radv_shader_module *module,
const char *entrypoint_name,
gl_shader_stage stage,
- const VkSpecializationInfo *spec_info);
+ const VkSpecializationInfo *spec_info,
+ const VkPipelineCreateFlags flags);
void *
radv_alloc_shader_memory(struct radv_device *device,
struct nir_shader *const *shaders,
int shader_count,
struct radv_pipeline_layout *layout,
- const struct ac_shader_variant_key *key,
+ const struct radv_shader_variant_key *key,
void **code_out,
unsigned *code_size_out);
static inline bool
radv_can_dump_shader(struct radv_device *device,
- struct radv_shader_module *module)
+ struct radv_shader_module *module,
+ bool is_gs_copy_shader)
{
+ if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
+ return false;
+
/* Only dump non-meta shaders, useful for debugging purposes. */
- return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS &&
- module && !module->nir;
+ return (module && !module->nir) || is_gs_copy_shader;
}
static inline bool
module && !module->nir;
}
+static inline unsigned shader_io_get_unique_index(gl_varying_slot slot)
+{
+ /* handle patch indices separate */
+ if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
+ return 0;
+ if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
+ return 1;
+ if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
+ return 2 + (slot - VARYING_SLOT_PATCH0);
+ if (slot == VARYING_SLOT_POS)
+ return 0;
+ if (slot == VARYING_SLOT_PSIZ)
+ return 1;
+ if (slot == VARYING_SLOT_CLIP_DIST0)
+ return 2;
+ /* 3 is reserved for clip dist as well */
+ if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
+ return 4 + (slot - VARYING_SLOT_VAR0);
+ unreachable("illegal slot in get unique index\n");
+}
+
+static inline uint32_t
+radv_get_num_physical_sgprs(struct radv_physical_device *physical_device)
+{
+ return physical_device->rad_info.chip_class >= VI ? 800 : 512;
+}
+
#endif
projects / mesa.git / blobdiff