radv: Add support for ETC2 textures.
[mesa.git] / src / amd / vulkan / radv_shader_info.c
index 47389d1b88bc4df76f2eab8394dd4c06da974f8e..8026cca46c868ebe518ff9ab15a8709a56baf8ce 100644 (file)
@@ -23,6 +23,7 @@
 #include "radv_private.h"
 #include "radv_shader.h"
 #include "nir/nir.h"
+#include "nir/nir_deref.h"
 
 static void mark_sampler_desc(const nir_variable *var,
                              struct radv_shader_info *info)
@@ -47,12 +48,136 @@ static void mark_tess_output(struct radv_shader_info *info,
                info->tcs.outputs_written |= (mask << param);
 }
 
+static void
+get_deref_offset(nir_deref_instr *instr,
+                 unsigned *const_out)
+{
+        nir_variable *var = nir_deref_instr_get_variable(instr);
+        nir_deref_path path;
+        unsigned idx_lvl = 1;
+
+       if (var->data.compact) {
+               assert(instr->deref_type == nir_deref_type_array);
+               nir_const_value *v = nir_src_as_const_value(instr->arr.index);
+               assert(v);
+               *const_out = v->u32[0];
+               return;
+       }
+
+       nir_deref_path_init(&path, instr, NULL);
+
+       uint32_t const_offset = 0;
+
+       for (; path.path[idx_lvl]; ++idx_lvl) {
+               const struct glsl_type *parent_type = path.path[idx_lvl - 1]->type;
+               if (path.path[idx_lvl]->deref_type == nir_deref_type_struct) {
+                       unsigned index = path.path[idx_lvl]->strct.index;
+
+                       for (unsigned i = 0; i < index; i++) {
+                               const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
+                               const_offset += glsl_count_attribute_slots(ft, false);
+                       }
+               } else if(path.path[idx_lvl]->deref_type == nir_deref_type_array) {
+                       unsigned size = glsl_count_attribute_slots(path.path[idx_lvl]->type, false);
+                       nir_const_value *v = nir_src_as_const_value(path.path[idx_lvl]->arr.index);
+                       if (v)
+                               const_offset += v->u32[0] * size;
+               } else
+                       unreachable("Uhandled deref type in get_deref_instr_offset");
+       }
+
+       *const_out = const_offset;
+
+       nir_deref_path_finish(&path);
+}
+
+static void
+gather_intrinsic_load_deref_info(const nir_shader *nir,
+                              const nir_intrinsic_instr *instr,
+                              struct radv_shader_info *info)
+{
+       switch (nir->info.stage) {
+       case MESA_SHADER_VERTEX: {
+               nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
+
+               if (var->data.mode == nir_var_shader_in) {
+                       unsigned idx = var->data.location;
+                       uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
+
+                       info->vs.input_usage_mask[idx] |=
+                               mask << var->data.location_frac;
+               }
+               break;
+       }
+       default:
+               break;
+       }
+}
+
+static void
+gather_intrinsic_store_deref_info(const nir_shader *nir,
+                               const nir_intrinsic_instr *instr,
+                               struct radv_shader_info *info)
+{
+       nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
+
+       if (var->data.mode == nir_var_shader_out) {
+               unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
+               unsigned idx = var->data.location;
+               unsigned comp = var->data.location_frac;
+               unsigned const_offset = 0;
+
+               get_deref_offset(nir_instr_as_deref(instr->src[0].ssa->parent_instr), &const_offset);
+
+               switch (nir->info.stage) {
+               case MESA_SHADER_VERTEX:
+                       for (unsigned i = 0; i < attrib_count; i++) {
+                               info->vs.output_usage_mask[idx + i + const_offset] |=
+                                       instr->const_index[0] << comp;
+                       }
+                       break;
+               case MESA_SHADER_GEOMETRY:
+                       for (unsigned i = 0; i < attrib_count; i++) {
+                               info->gs.output_usage_mask[idx + i + const_offset] |=
+                                       instr->const_index[0] << comp;
+                       }
+                       break;
+               case MESA_SHADER_TESS_EVAL:
+                       for (unsigned i = 0; i < attrib_count; i++) {
+                               info->tes.output_usage_mask[idx + i + const_offset] |=
+                                       instr->const_index[0] << comp;
+                       }
+                       break;
+               case MESA_SHADER_TESS_CTRL: {
+                       unsigned param = shader_io_get_unique_index(idx);
+                       const struct glsl_type *type = var->type;
+
+                       if (!var->data.patch)
+                               type = glsl_get_array_element(var->type);
+
+                       unsigned slots =
+                               var->data.compact ? DIV_ROUND_UP(glsl_get_length(type), 4)
+                                                 : glsl_count_attribute_slots(type, false);
+
+                       if (idx == VARYING_SLOT_CLIP_DIST0)
+                               slots = (nir->info.clip_distance_array_size +
+                                        nir->info.cull_distance_array_size > 4) ? 2 : 1;
+
+                       mark_tess_output(info, var->data.patch, param, slots);
+                       break;
+               }
+               default:
+                       break;
+               }
+       }
+}
+
 static void
 gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
                      struct radv_shader_info *info)
 {
        switch (instr->intrinsic) {
-       case nir_intrinsic_interp_var_at_sample:
+       case nir_intrinsic_interp_deref_at_sample:
                info->ps.needs_sample_positions = true;
                break;
        case nir_intrinsic_load_draw_id:
@@ -105,20 +230,19 @@ gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
        case nir_intrinsic_vulkan_resource_index:
                info->desc_set_used_mask |= (1 << nir_intrinsic_desc_set(instr));
                break;
-       case nir_intrinsic_image_var_load:
-       case nir_intrinsic_image_var_store:
-       case nir_intrinsic_image_var_atomic_add:
-       case nir_intrinsic_image_var_atomic_min:
-       case nir_intrinsic_image_var_atomic_max:
-       case nir_intrinsic_image_var_atomic_and:
-       case nir_intrinsic_image_var_atomic_or:
-       case nir_intrinsic_image_var_atomic_xor:
-       case nir_intrinsic_image_var_atomic_exchange:
-       case nir_intrinsic_image_var_atomic_comp_swap:
-       case nir_intrinsic_image_var_size: {
-               const struct glsl_type *type = instr->variables[0]->var->type;
-               if(instr->variables[0]->deref.child)
-                       type = instr->variables[0]->deref.child->type;
+       case nir_intrinsic_image_deref_load:
+       case nir_intrinsic_image_deref_store:
+       case nir_intrinsic_image_deref_atomic_add:
+       case nir_intrinsic_image_deref_atomic_min:
+       case nir_intrinsic_image_deref_atomic_max:
+       case nir_intrinsic_image_deref_atomic_and:
+       case nir_intrinsic_image_deref_atomic_or:
+       case nir_intrinsic_image_deref_atomic_xor:
+       case nir_intrinsic_image_deref_atomic_exchange:
+       case nir_intrinsic_image_deref_atomic_comp_swap:
+       case nir_intrinsic_image_deref_size: {
+               nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
+               const struct glsl_type *type = glsl_without_array(var->type);
 
                enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
                if (dim == GLSL_SAMPLER_DIM_SUBPASS ||
@@ -126,17 +250,17 @@ gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
                        info->ps.layer_input = true;
                        info->ps.uses_input_attachments = true;
                }
-               mark_sampler_desc(instr->variables[0]->var, info);
-
-               if (nir_intrinsic_image_var_store ||
-                   nir_intrinsic_image_var_atomic_add ||
-                   nir_intrinsic_image_var_atomic_min ||
-                   nir_intrinsic_image_var_atomic_max ||
-                   nir_intrinsic_image_var_atomic_and ||
-                   nir_intrinsic_image_var_atomic_or ||
-                   nir_intrinsic_image_var_atomic_xor ||
-                   nir_intrinsic_image_var_atomic_exchange ||
-                   nir_intrinsic_image_var_atomic_comp_swap) {
+               mark_sampler_desc(var, info);
+
+               if (nir_intrinsic_image_deref_store ||
+                   nir_intrinsic_image_deref_atomic_add ||
+                   nir_intrinsic_image_deref_atomic_min ||
+                   nir_intrinsic_image_deref_atomic_max ||
+                   nir_intrinsic_image_deref_atomic_and ||
+                   nir_intrinsic_image_deref_atomic_or ||
+                   nir_intrinsic_image_deref_atomic_xor ||
+                   nir_intrinsic_image_deref_atomic_exchange ||
+                   nir_intrinsic_image_deref_atomic_comp_swap) {
                        if (nir->info.stage == MESA_SHADER_FRAGMENT)
                                info->ps.writes_memory = true;
                }
@@ -156,48 +280,12 @@ gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
                if (nir->info.stage == MESA_SHADER_FRAGMENT)
                        info->ps.writes_memory = true;
                break;
-       case nir_intrinsic_load_var:
-               if (nir->info.stage == MESA_SHADER_VERTEX) {
-                       nir_deref_var *dvar = instr->variables[0];
-                       nir_variable *var = dvar->var;
-
-                       if (var->data.mode == nir_var_shader_in) {
-                               unsigned idx = var->data.location;
-                               uint8_t mask =
-                                       nir_ssa_def_components_read(&instr->dest.ssa) << var->data.location_frac;
-                               info->vs.input_usage_mask[idx] |= mask;
-                       }
-               }
+       case nir_intrinsic_load_deref:
+               gather_intrinsic_load_deref_info(nir, instr, info);
                break;
-       case nir_intrinsic_store_var: {
-               nir_deref_var *dvar = instr->variables[0];
-               nir_variable *var = dvar->var;
-
-               if (var->data.mode == nir_var_shader_out) {
-                       unsigned idx = var->data.location;
-                       unsigned comp = var->data.location_frac;
-
-                       if (nir->info.stage == MESA_SHADER_VERTEX) {
-                               info->vs.output_usage_mask[idx] |=
-                                       instr->const_index[0] << comp;
-                       } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
-                               info->tes.output_usage_mask[idx] |=
-                                       instr->const_index[0] << comp;
-                       } else if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
-                               unsigned param = shader_io_get_unique_index(idx);
-                               const struct glsl_type *type = var->type;
-                               if (!var->data.patch)
-                                       type = glsl_get_array_element(var->type);
-                               unsigned slots =
-                                       var->data.compact ? DIV_ROUND_UP(glsl_get_length(type), 4)
-                                       : glsl_count_attribute_slots(type, false);
-                               if (idx == VARYING_SLOT_CLIP_DIST0)
-                                       slots = (nir->info.clip_distance_array_size + nir->info.cull_distance_array_size > 4) ? 2 : 1;
-                               mark_tess_output(info, var->data.patch, param, slots);
-                       }
-               }
+       case nir_intrinsic_store_deref:
+               gather_intrinsic_store_deref_info(nir, instr, info);
                break;
-       }
        default:
                break;
        }
@@ -207,10 +295,18 @@ static void
 gather_tex_info(const nir_shader *nir, const nir_tex_instr *instr,
                struct radv_shader_info *info)
 {
-       if (instr->sampler)
-               mark_sampler_desc(instr->sampler->var, info);
-       if (instr->texture)
-               mark_sampler_desc(instr->texture->var, info);
+       for (unsigned i = 0; i < instr->num_srcs; i++) {
+               switch (instr->src[i].src_type) {
+               case nir_tex_src_texture_deref:
+                       mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src)), info);
+                       break;
+               case nir_tex_src_sampler_deref:
+                       mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src)), info);
+                       break;
+               default:
+                       break;
+               }
+       }
 }
 
 static void
@@ -343,7 +439,7 @@ radv_nir_shader_info_pass(const struct nir_shader *nir,
        struct nir_function *func =
                (struct nir_function *)exec_list_get_head_const(&nir->functions);
 
-       if (options->layout->dynamic_offset_count)
+       if (options->layout && options->layout->dynamic_offset_count)
                info->loads_push_constants = true;
 
        nir_foreach_variable(variable, &nir->inputs)