radv: add set_loc_shader_ptr() helper
[mesa.git] / src / amd / vulkan / radv_shader_info.c
index 47389d1b88bc4df76f2eab8394dd4c06da974f8e..b45b4c0c95b723be30fe5341b97748db28aa1868 100644 (file)
@@ -47,6 +47,129 @@ static void mark_tess_output(struct radv_shader_info *info,
                info->tcs.outputs_written |= (mask << param);
 }
 
+static void get_deref_offset(nir_deref_var *deref, unsigned *const_out)
+{
+       nir_deref *tail = &deref->deref;
+       unsigned const_offset = 0;
+
+       if (deref->var->data.compact) {
+               assert(tail->child->deref_type == nir_deref_type_array);
+               assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
+
+               nir_deref_array *deref_array = nir_deref_as_array(tail->child);
+               /* We always lower indirect dereferences for "compact" array vars. */
+               assert(deref_array->deref_array_type == nir_deref_array_type_direct);
+
+               *const_out = deref_array->base_offset;
+               return;
+       }
+
+       while (tail->child != NULL) {
+               const struct glsl_type *parent_type = tail->type;
+               tail = tail->child;
+
+               if (tail->deref_type == nir_deref_type_array) {
+                       nir_deref_array *deref_array = nir_deref_as_array(tail);
+                       unsigned size = glsl_count_attribute_slots(tail->type, false);
+
+                       const_offset += size * deref_array->base_offset;
+               } else if (tail->deref_type == nir_deref_type_struct) {
+                       nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
+
+                       for (unsigned i = 0; i < deref_struct->index; i++) {
+                               const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
+                               const_offset += glsl_count_attribute_slots(ft, false);
+                       }
+               } else
+                       unreachable("unsupported deref type");
+       }
+
+       *const_out = const_offset;
+}
+
+static void
+gather_intrinsic_load_var_info(const nir_shader *nir,
+                              const nir_intrinsic_instr *instr,
+                              struct radv_shader_info *info)
+{
+       switch (nir->info.stage) {
+       case MESA_SHADER_VERTEX: {
+               nir_deref_var *dvar = instr->variables[0];
+               nir_variable *var = dvar->var;
+
+               if (var->data.mode == nir_var_shader_in) {
+                       unsigned idx = var->data.location;
+                       uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
+
+                       info->vs.input_usage_mask[idx] |=
+                               mask << var->data.location_frac;
+               }
+               break;
+       }
+       default:
+               break;
+       }
+}
+
+static void
+gather_intrinsic_store_var_info(const nir_shader *nir,
+                               const nir_intrinsic_instr *instr,
+                               struct radv_shader_info *info)
+{
+       nir_deref_var *dvar = instr->variables[0];
+       nir_variable *var = dvar->var;
+
+       if (var->data.mode == nir_var_shader_out) {
+               unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
+               unsigned idx = var->data.location;
+               unsigned comp = var->data.location_frac;
+               unsigned const_offset = 0;
+
+               get_deref_offset(dvar, &const_offset);
+
+               switch (nir->info.stage) {
+               case MESA_SHADER_VERTEX:
+                       for (unsigned i = 0; i < attrib_count; i++) {
+                               info->vs.output_usage_mask[idx + i + const_offset] |=
+                                       instr->const_index[0] << comp;
+                       }
+                       break;
+               case MESA_SHADER_GEOMETRY:
+                       for (unsigned i = 0; i < attrib_count; i++) {
+                               info->gs.output_usage_mask[idx + i + const_offset] |=
+                                       instr->const_index[0] << comp;
+                       }
+                       break;
+               case MESA_SHADER_TESS_EVAL:
+                       for (unsigned i = 0; i < attrib_count; i++) {
+                               info->tes.output_usage_mask[idx + i + const_offset] |=
+                                       instr->const_index[0] << comp;
+                       }
+                       break;
+               case MESA_SHADER_TESS_CTRL: {
+                       unsigned param = shader_io_get_unique_index(idx);
+                       const struct glsl_type *type = var->type;
+
+                       if (!var->data.patch)
+                               type = glsl_get_array_element(var->type);
+
+                       unsigned slots =
+                               var->data.compact ? DIV_ROUND_UP(glsl_get_length(type), 4)
+                                                 : glsl_count_attribute_slots(type, false);
+
+                       if (idx == VARYING_SLOT_CLIP_DIST0)
+                               slots = (nir->info.clip_distance_array_size +
+                                        nir->info.cull_distance_array_size > 4) ? 2 : 1;
+
+                       mark_tess_output(info, var->data.patch, param, slots);
+                       break;
+               }
+               default:
+                       break;
+               }
+       }
+}
+
 static void
 gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
                      struct radv_shader_info *info)
@@ -157,47 +280,11 @@ gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
                        info->ps.writes_memory = true;
                break;
        case nir_intrinsic_load_var:
-               if (nir->info.stage == MESA_SHADER_VERTEX) {
-                       nir_deref_var *dvar = instr->variables[0];
-                       nir_variable *var = dvar->var;
-
-                       if (var->data.mode == nir_var_shader_in) {
-                               unsigned idx = var->data.location;
-                               uint8_t mask =
-                                       nir_ssa_def_components_read(&instr->dest.ssa) << var->data.location_frac;
-                               info->vs.input_usage_mask[idx] |= mask;
-                       }
-               }
+               gather_intrinsic_load_var_info(nir, instr, info);
                break;
-       case nir_intrinsic_store_var: {
-               nir_deref_var *dvar = instr->variables[0];
-               nir_variable *var = dvar->var;
-
-               if (var->data.mode == nir_var_shader_out) {
-                       unsigned idx = var->data.location;
-                       unsigned comp = var->data.location_frac;
-
-                       if (nir->info.stage == MESA_SHADER_VERTEX) {
-                               info->vs.output_usage_mask[idx] |=
-                                       instr->const_index[0] << comp;
-                       } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
-                               info->tes.output_usage_mask[idx] |=
-                                       instr->const_index[0] << comp;
-                       } else if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
-                               unsigned param = shader_io_get_unique_index(idx);
-                               const struct glsl_type *type = var->type;
-                               if (!var->data.patch)
-                                       type = glsl_get_array_element(var->type);
-                               unsigned slots =
-                                       var->data.compact ? DIV_ROUND_UP(glsl_get_length(type), 4)
-                                       : glsl_count_attribute_slots(type, false);
-                               if (idx == VARYING_SLOT_CLIP_DIST0)
-                                       slots = (nir->info.clip_distance_array_size + nir->info.cull_distance_array_size > 4) ? 2 : 1;
-                               mark_tess_output(info, var->data.patch, param, slots);
-                       }
-               }
+       case nir_intrinsic_store_var:
+               gather_intrinsic_store_var_info(nir, instr, info);
                break;
-       }
        default:
                break;
        }
@@ -343,7 +430,7 @@ radv_nir_shader_info_pass(const struct nir_shader *nir,
        struct nir_function *func =
                (struct nir_function *)exec_list_get_head_const(&nir->functions);
 
-       if (options->layout->dynamic_offset_count)
+       if (options->layout && options->layout->dynamic_offset_count)
                info->loads_push_constants = true;
 
        nir_foreach_variable(variable, &nir->inputs)