radv: do not pass all compiler options to the shader info pass
[mesa.git] / src / amd / vulkan / radv_shader_info.c
index 2756d99e7696cf70548b0b25a37d6563737e29db..b839d20f1e05ed0500dc9b2f5d326060ffeead7c 100644 (file)
@@ -284,8 +284,10 @@ gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
        case nir_intrinsic_image_deref_load:
        case nir_intrinsic_image_deref_store:
        case nir_intrinsic_image_deref_atomic_add:
-       case nir_intrinsic_image_deref_atomic_min:
-       case nir_intrinsic_image_deref_atomic_max:
+       case nir_intrinsic_image_deref_atomic_imin:
+       case nir_intrinsic_image_deref_atomic_umin:
+       case nir_intrinsic_image_deref_atomic_imax:
+       case nir_intrinsic_image_deref_atomic_umax:
        case nir_intrinsic_image_deref_atomic_and:
        case nir_intrinsic_image_deref_atomic_or:
        case nir_intrinsic_image_deref_atomic_xor:
@@ -297,8 +299,10 @@ gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
 
                if (instr->intrinsic == nir_intrinsic_image_deref_store ||
                    instr->intrinsic == nir_intrinsic_image_deref_atomic_add ||
-                   instr->intrinsic == nir_intrinsic_image_deref_atomic_min ||
-                   instr->intrinsic == nir_intrinsic_image_deref_atomic_max ||
+                   instr->intrinsic == nir_intrinsic_image_deref_atomic_imin ||
+                   instr->intrinsic == nir_intrinsic_image_deref_atomic_umin ||
+                   instr->intrinsic == nir_intrinsic_image_deref_atomic_imax ||
+                   instr->intrinsic == nir_intrinsic_image_deref_atomic_umax ||
                    instr->intrinsic == nir_intrinsic_image_deref_atomic_and ||
                    instr->intrinsic == nir_intrinsic_image_deref_atomic_or ||
                    instr->intrinsic == nir_intrinsic_image_deref_atomic_xor ||
@@ -373,7 +377,7 @@ gather_info_block(const nir_shader *nir, const nir_block *block,
 static void
 gather_info_input_decl_vs(const nir_shader *nir, const nir_variable *var,
                          struct radv_shader_info *info,
-                         const struct radv_nir_compiler_options *options)
+                         const struct radv_shader_variant_key *key)
 {
        unsigned attrib_count = glsl_count_attribute_slots(var->type, true);
        int idx = var->data.location;
@@ -384,11 +388,33 @@ gather_info_input_decl_vs(const nir_shader *nir, const nir_variable *var,
        for (unsigned i = 0; i < attrib_count; ++i) {
                unsigned attrib_index = var->data.location + i - VERT_ATTRIB_GENERIC0;
 
-               if (options->key.vs.instance_rate_inputs & (1u << attrib_index))
+               if (key->vs.instance_rate_inputs & (1u << attrib_index))
                        info->vs.needs_instance_id = true;
        }
 }
 
+static void
+mark_16bit_ps_input(struct radv_shader_info *info, const struct glsl_type *type,
+                   int location)
+{
+       if (glsl_type_is_scalar(type) || glsl_type_is_vector(type) || glsl_type_is_matrix(type)) {
+               unsigned attrib_count = glsl_count_attribute_slots(type, false);
+               if (glsl_type_is_16bit(type)) {
+                       info->ps.float16_shaded_mask |= ((1ull << attrib_count) - 1) << location;
+               }
+       } else if (glsl_type_is_array(type)) {
+               unsigned stride = glsl_count_attribute_slots(glsl_get_array_element(type), false);
+               for (unsigned i = 0; i < glsl_get_length(type); ++i) {
+                       mark_16bit_ps_input(info, glsl_get_array_element(type), location + i * stride);
+               }
+       } else {
+               assert(glsl_type_is_struct_or_ifc(type));
+               for (unsigned i = 0; i < glsl_get_length(type); i++) {
+                       mark_16bit_ps_input(info, glsl_get_struct_field(type, i), location);
+                       location += glsl_count_attribute_slots(glsl_get_struct_field(type, i), false);
+               }
+       }
+}
 static void
 gather_info_input_decl_ps(const nir_shader *nir, const nir_variable *var,
                          struct radv_shader_info *info)
@@ -419,16 +445,32 @@ gather_info_input_decl_ps(const nir_shader *nir, const nir_variable *var,
                if (var->data.sample)
                        info->ps.force_persample = true;
        }
+
+       if (var->data.compact) {
+               unsigned component_count = var->data.location_frac +
+                                          glsl_get_length(var->type);
+               attrib_count = (component_count + 3) / 4;
+       } else {
+               mark_16bit_ps_input(info, var->type, var->data.driver_location);
+       }
+
+       uint64_t mask = ((1ull << attrib_count) - 1);
+
+       if (var->data.interpolation == INTERP_MODE_FLAT)
+               info->ps.flat_shaded_mask |= mask << var->data.driver_location;
+
+       if (var->data.location >= VARYING_SLOT_VAR0)
+               info->ps.input_mask |= mask << (var->data.location - VARYING_SLOT_VAR0);
 }
 
 static void
 gather_info_input_decl(const nir_shader *nir, const nir_variable *var,
                       struct radv_shader_info *info,
-                      const struct radv_nir_compiler_options *options)
+                      const struct radv_shader_variant_key *key)
 {
        switch (nir->info.stage) {
        case MESA_SHADER_VERTEX:
-               gather_info_input_decl_vs(nir, var, info, options);
+               gather_info_input_decl_vs(nir, var, info, key);
                break;
        case MESA_SHADER_FRAGMENT:
                gather_info_input_decl_ps(nir, var, info);
@@ -489,22 +531,56 @@ gather_info_output_decl_gs(const nir_shader *nir, const nir_variable *var,
 static void
 gather_info_output_decl(const nir_shader *nir, const nir_variable *var,
                        struct radv_shader_info *info,
-                       const struct radv_nir_compiler_options *options)
+                       const struct radv_shader_variant_key *key)
 {
+       struct radv_vs_output_info *vs_info = NULL;
+
        switch (nir->info.stage) {
        case MESA_SHADER_FRAGMENT:
                gather_info_output_decl_ps(nir, var, info);
                break;
        case MESA_SHADER_VERTEX:
-               if (options->key.vs_common_out.as_ls)
+               if (!key->vs_common_out.as_ls &&
+                   !key->vs_common_out.as_es)
+                       vs_info = &info->vs.outinfo;
+
+               if (key->vs_common_out.as_ls)
                        gather_info_output_decl_ls(nir, var, info);
                break;
        case MESA_SHADER_GEOMETRY:
+               vs_info = &info->vs.outinfo;
                gather_info_output_decl_gs(nir, var, info);
                break;
+       case MESA_SHADER_TESS_EVAL:
+               if (!key->vs_common_out.as_es)
+                       vs_info = &info->tes.outinfo;
+               break;
        default:
                break;
        }
+
+       if (vs_info) {
+               switch (var->data.location) {
+               case VARYING_SLOT_CLIP_DIST0:
+                       vs_info->clip_dist_mask =
+                               (1 << nir->info.clip_distance_array_size) - 1;
+                       vs_info->cull_dist_mask =
+                               (1 << nir->info.cull_distance_array_size) - 1;
+                       vs_info->cull_dist_mask <<= nir->info.clip_distance_array_size;
+                       break;
+               case VARYING_SLOT_PSIZ:
+                       vs_info->writes_pointsize = true;
+                       break;
+               case VARYING_SLOT_VIEWPORT:
+                       vs_info->writes_viewport_index = true;
+                       break;
+               case VARYING_SLOT_LAYER:
+                       vs_info->writes_layer = true;
+                       break;
+               default:
+                       break;
+               }
+       }
 }
 
 static void
@@ -550,30 +626,152 @@ radv_nir_shader_info_init(struct radv_shader_info *info)
 
 void
 radv_nir_shader_info_pass(const struct nir_shader *nir,
-                         const struct radv_nir_compiler_options *options,
+                         const struct radv_pipeline_layout *layout,
+                         const struct radv_shader_variant_key *key,
                          struct radv_shader_info *info)
 {
        struct nir_function *func =
                (struct nir_function *)exec_list_get_head_const(&nir->functions);
 
-       if (options->layout && options->layout->dynamic_offset_count &&
-           (options->layout->dynamic_shader_stages & mesa_to_vk_shader_stage(nir->info.stage))) {
+       if (layout && layout->dynamic_offset_count &&
+           (layout->dynamic_shader_stages & mesa_to_vk_shader_stage(nir->info.stage))) {
                info->loads_push_constants = true;
                info->loads_dynamic_offsets = true;
        }
 
        nir_foreach_variable(variable, &nir->inputs)
-               gather_info_input_decl(nir, variable, info, options);
+               gather_info_input_decl(nir, variable, info, key);
 
        nir_foreach_block(block, func->impl) {
                gather_info_block(nir, block, info);
        }
 
        nir_foreach_variable(variable, &nir->outputs)
-               gather_info_output_decl(nir, variable, info, options);
+               gather_info_output_decl(nir, variable, info, key);
 
        if (nir->info.stage == MESA_SHADER_VERTEX ||
            nir->info.stage == MESA_SHADER_TESS_EVAL ||
            nir->info.stage == MESA_SHADER_GEOMETRY)
                gather_xfb_info(nir, info);
+
+       /* Make sure to export the LayerID if the fragment shader needs it. */
+       if (key->vs_common_out.export_layer_id) {
+               switch (nir->info.stage) {
+               case MESA_SHADER_VERTEX:
+                       info->vs.output_usage_mask[VARYING_SLOT_LAYER] |= 0x1;
+                       break;
+               case MESA_SHADER_TESS_EVAL:
+                       info->tes.output_usage_mask[VARYING_SLOT_LAYER] |= 0x1;
+                       break;
+               case MESA_SHADER_GEOMETRY:
+                       info->gs.output_usage_mask[VARYING_SLOT_LAYER] |= 0x1;
+                       break;
+               default:
+                       break;
+               }
+       }
+
+       /* Make sure to export the LayerID if the subpass has multiviews. */
+       if (key->has_multiview_view_index) {
+               switch (nir->info.stage) {
+               case MESA_SHADER_VERTEX:
+                       info->vs.outinfo.writes_layer = true;
+                       break;
+               case MESA_SHADER_TESS_EVAL:
+                       info->tes.outinfo.writes_layer = true;
+                       break;
+               case MESA_SHADER_GEOMETRY:
+                       info->vs.outinfo.writes_layer = true;
+                       break;
+               default:
+                       break;
+               }
+       }
+
+       /* Make sure to export the PrimitiveID if the fragment shader needs it. */
+       if (key->vs_common_out.export_prim_id) {
+               switch (nir->info.stage) {
+               case MESA_SHADER_VERTEX:
+                       info->vs.outinfo.export_prim_id = true;
+                       break;
+               case MESA_SHADER_TESS_EVAL:
+                       info->tes.outinfo.export_prim_id = true;
+                       break;
+               case MESA_SHADER_GEOMETRY:
+                       info->vs.outinfo.export_prim_id = true;
+                       break;
+               default:
+                       break;
+               }
+       }
+
+       if (nir->info.stage == MESA_SHADER_FRAGMENT)
+               info->ps.num_interp = nir->num_inputs;
+
+       switch (nir->info.stage) {
+        case MESA_SHADER_COMPUTE:
+                for (int i = 0; i < 3; ++i)
+                        info->cs.block_size[i] = nir->info.cs.local_size[i];
+                break;
+        case MESA_SHADER_FRAGMENT:
+               info->ps.can_discard = nir->info.fs.uses_discard;
+                info->ps.early_fragment_test = nir->info.fs.early_fragment_tests;
+                info->ps.post_depth_coverage = nir->info.fs.post_depth_coverage;
+                break;
+        case MESA_SHADER_GEOMETRY:
+                info->gs.vertices_in = nir->info.gs.vertices_in;
+                info->gs.vertices_out = nir->info.gs.vertices_out;
+                info->gs.output_prim = nir->info.gs.output_primitive;
+                info->gs.invocations = nir->info.gs.invocations;
+                break;
+        case MESA_SHADER_TESS_EVAL:
+                info->tes.primitive_mode = nir->info.tess.primitive_mode;
+                info->tes.spacing = nir->info.tess.spacing;
+                info->tes.ccw = nir->info.tess.ccw;
+                info->tes.point_mode = nir->info.tess.point_mode;
+                info->tes.as_es = key->vs_common_out.as_es;
+                info->tes.export_prim_id = key->vs_common_out.export_prim_id;
+                info->is_ngg = key->vs_common_out.as_ngg;
+                break;
+        case MESA_SHADER_TESS_CTRL:
+                info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
+                break;
+        case MESA_SHADER_VERTEX:
+                info->vs.as_es = key->vs_common_out.as_es;
+                info->vs.as_ls = key->vs_common_out.as_ls;
+                info->vs.export_prim_id = key->vs_common_out.export_prim_id;
+                info->is_ngg = key->vs_common_out.as_ngg;
+                break;
+        default:
+                break;
+        }
+
+       if (nir->info.stage == MESA_SHADER_GEOMETRY) {
+               unsigned add_clip = nir->info.clip_distance_array_size +
+                                   nir->info.cull_distance_array_size > 4;
+               info->gs.gsvs_vertex_size =
+                       (util_bitcount64(nir->info.outputs_written) + add_clip) * 16;
+               info->gs.max_gsvs_emit_size =
+                       info->gs.gsvs_vertex_size * nir->info.gs.vertices_out;
+       }
+
+       /* Compute the ESGS item size for VS or TES as ES. */
+       if ((nir->info.stage == MESA_SHADER_VERTEX ||
+            nir->info.stage == MESA_SHADER_TESS_EVAL) &&
+           key->vs_common_out.as_es) {
+               struct radv_es_output_info *es_info =
+                       nir->info.stage == MESA_SHADER_VERTEX ? &info->vs.es_info : &info->tes.es_info;
+               uint32_t max_output_written = 0;
+
+               uint64_t output_mask = nir->info.outputs_written;
+               while (output_mask) {
+                       const int i = u_bit_scan64(&output_mask);
+                       unsigned param_index = shader_io_get_unique_index(i);
+
+                       max_output_written = MAX2(param_index, max_output_written);
+               }
+
+               es_info->esgs_itemsize = (max_output_written + 1) * 16;
+       }
+
 }