radv: align the LDS size in calculate_tess_lds_size()

[mesa.git] / src / amd / vulkan / radv_shader_info.c

diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c
index dc4aea1d2198bb141007128b9123a1164773aad2..eca46c811578c44fa102fced0c278fd26190832c 100644 (file)
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -668,7 +668,7 @@ radv_nir_shader_info_pass(const struct nir_shader *nir,
                          const struct radv_pipeline_layout *layout,
                          const struct radv_shader_variant_key *key,
                          struct radv_shader_info *info,
-                         bool use_aco)
+                         bool use_llvm)
 {
        struct nir_function *func =
                (struct nir_function *)exec_list_get_head_const(&nir->functions);
@@ -822,13 +822,7 @@ radv_nir_shader_info_pass(const struct nir_shader *nir,
                struct radv_es_output_info *es_info =
                        nir->info.stage == MESA_SHADER_VERTEX ? &info->vs.es_info : &info->tes.es_info;
 
-               if (use_aco) {
-                       /* The outputs don't contain gaps, se we can use the number of outputs */
-                       uint32_t num_outputs_written = nir->info.stage == MESA_SHADER_VERTEX
-                               ? info->vs.num_linked_outputs
-                               : info->tes.num_linked_outputs;
-                       es_info->esgs_itemsize = num_outputs_written * 16;
-               } else {
+               if (use_llvm) {
                        /* The outputs may contain gaps, use the highest output index + 1 */
                        uint32_t max_output_written = 0;
                        uint64_t output_mask = nir->info.outputs_written;
@@ -839,8 +833,13 @@ radv_nir_shader_info_pass(const struct nir_shader *nir,
 
                                max_output_written = MAX2(param_index, max_output_written);
                        }
-
                        es_info->esgs_itemsize = (max_output_written + 1) * 16;
+               } else {
+                       /* The outputs don't contain gaps, se we can use the number of outputs */
+                       uint32_t num_outputs_written = nir->info.stage == MESA_SHADER_VERTEX
+                               ? info->vs.num_linked_outputs
+                               : info->tes.num_linked_outputs;
+                       es_info->esgs_itemsize = num_outputs_written * 16;
                }
        }
 
@@ -858,5 +857,9 @@ radv_nir_shader_info_pass(const struct nir_shader *nir,
                                info->ps.cb_shader_mask |= 0xf << (i * 4);
                        }
                }
+
+               if (key->fs.is_dual_src) {
+                       info->ps.cb_shader_mask |= (info->ps.cb_shader_mask & 0xf) << 4;
+               }
        }
 }