default:
break;
}
+
+ if (idx >= FRAG_RESULT_DATA0 && idx <= FRAG_RESULT_DATA7) {
+ unsigned num_components = glsl_get_component_slots(glsl_without_array(var->type));
+ unsigned num_slots = glsl_count_attribute_slots(var->type, false);
+ unsigned write_mask = (1 << num_components) - 1;
+ unsigned slot = idx - FRAG_RESULT_DATA0;
+
+ for (unsigned i = 0; i < num_slots; i++) {
+ info->ps.cb_shader_mask |= write_mask << ((slot + i) * 4);
+ }
+ }
}
static void
radv_nir_shader_info_pass(const struct nir_shader *nir,
const struct radv_pipeline_layout *layout,
const struct radv_shader_variant_key *key,
- struct radv_shader_info *info)
+ struct radv_shader_info *info,
+ bool use_llvm)
{
struct nir_function *func =
(struct nir_function *)exec_list_get_head_const(&nir->functions);
info->ps.can_discard = nir->info.fs.uses_discard;
info->ps.early_fragment_test = nir->info.fs.early_fragment_tests;
info->ps.post_depth_coverage = nir->info.fs.post_depth_coverage;
+ info->ps.depth_layout = nir->info.fs.depth_layout;
break;
case MESA_SHADER_GEOMETRY:
info->gs.vertices_in = nir->info.gs.vertices_in;
key->vs_common_out.as_es) {
struct radv_es_output_info *es_info =
nir->info.stage == MESA_SHADER_VERTEX ? &info->vs.es_info : &info->tes.es_info;
- uint32_t max_output_written = 0;
- uint64_t output_mask = nir->info.outputs_written;
- while (output_mask) {
- const int i = u_bit_scan64(&output_mask);
- unsigned param_index = shader_io_get_unique_index(i);
+ if (use_llvm) {
+ /* The outputs may contain gaps, use the highest output index + 1 */
+ uint32_t max_output_written = 0;
+ uint64_t output_mask = nir->info.outputs_written;
- max_output_written = MAX2(param_index, max_output_written);
- }
+ while (output_mask) {
+ const int i = u_bit_scan64(&output_mask);
+ unsigned param_index = shader_io_get_unique_index(i);
- es_info->esgs_itemsize = (max_output_written + 1) * 16;
+ max_output_written = MAX2(param_index, max_output_written);
+ }
+ es_info->esgs_itemsize = (max_output_written + 1) * 16;
+ } else {
+ /* The outputs don't contain gaps, se we can use the number of outputs */
+ uint32_t num_outputs_written = nir->info.stage == MESA_SHADER_VERTEX
+ ? info->vs.num_linked_outputs
+ : info->tes.num_linked_outputs;
+ es_info->esgs_itemsize = num_outputs_written * 16;
+ }
}
info->float_controls_mode = nir->info.float_controls_execution_mode;
+
+ if (nir->info.stage == MESA_SHADER_FRAGMENT) {
+ /* If the i-th output is used, all previous outputs must be
+ * non-zero to match the target format.
+ * TODO: compact MRT to avoid holes and to remove this
+ * workaround.
+ */
+ unsigned num_targets = (util_last_bit(info->ps.cb_shader_mask) + 3) / 4;
+ for (unsigned i = 0; i < num_targets; i++) {
+ if (!(info->ps.cb_shader_mask & (0xf << (i * 4)))) {
+ info->ps.cb_shader_mask |= 0xf << (i * 4);
+ }
+ }
+
+ if (key->fs.is_dual_src) {
+ info->ps.cb_shader_mask |= (info->ps.cb_shader_mask & 0xf) << 4;
+ }
+ }
}