static void
si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
- struct radeon_winsys_cs *cs,
+ struct radeon_cmdbuf *cs,
unsigned raster_config,
unsigned raster_config_1)
{
static void
si_emit_compute(struct radv_physical_device *physical_device,
- struct radeon_winsys_cs *cs)
+ struct radeon_cmdbuf *cs)
{
radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
radeon_emit(cs, 0);
static void
si_set_raster_config(struct radv_physical_device *physical_device,
- struct radeon_winsys_cs *cs)
+ struct radeon_cmdbuf *cs)
{
unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
static void
si_emit_config(struct radv_physical_device *physical_device,
- struct radeon_winsys_cs *cs)
+ struct radeon_cmdbuf *cs)
{
int i;
void
cik_create_gfx_config(struct radv_device *device)
{
- struct radeon_winsys_cs *cs = device->ws->cs_create(device->ws, RING_GFX);
+ struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX);
if (!cs)
return;
}
void
-si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
+si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
int count, const VkViewport *viewports)
{
int i;
}
void
-si_write_scissors(struct radeon_winsys_cs *cs, int first,
+si_write_scissors(struct radeon_cmdbuf *cs, int first,
int count, const VkRect2D *scissors,
const VkViewport *viewports, bool can_use_guardband)
{
}
-void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
+void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
bool predicated,
enum chip_class chip_class,
bool is_mec,
}
void
-si_emit_wait_fence(struct radeon_winsys_cs *cs,
+si_emit_wait_fence(struct radeon_cmdbuf *cs,
bool predicated,
uint64_t va, uint32_t ref,
uint32_t mask)
}
static void
-si_emit_acquire_mem(struct radeon_winsys_cs *cs,
+si_emit_acquire_mem(struct radeon_cmdbuf *cs,
bool is_mec,
bool predicated,
bool is_gfx9,
}
void
-si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
+si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
enum chip_class chip_class,
uint32_t *flush_cnt,
uint64_t flush_va,
uint64_t dst_va, uint64_t src_va,
unsigned size, unsigned flags)
{
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radeon_cmdbuf *cs = cmd_buffer->cs;
uint32_t header = 0, command = 0;
assert(size);
return max_dist[log_samples];
}
-void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples)
+void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples)
{
switch (nr_samples) {
default: