radv: move calculating primgroup_size to pipeline.

[mesa.git] / src / amd / vulkan / si_cmd_buffer.c

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 2102c0a30bec3c90bc549c7a72411672da42716a..9abd05583c52be978915355516e865175b1cbc76 100644 (file)
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -683,7 +683,6 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
        enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
        struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
        unsigned prim = cmd_buffer->state.pipeline->graphics.prim;
-       unsigned primgroup_size = 128; /* recommended without a GS */
        unsigned max_primgroup_in_wave = 2;
        /* SWITCH_ON_EOP(0) is always preferable. */
        bool wd_switch_on_eop = false;
@@ -691,16 +690,15 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
        bool ia_switch_on_eoi = false;
        bool partial_vs_wave = false;
        bool partial_es_wave = false;
-       uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
        bool multi_instances_smaller_than_primgroup;
 
-       if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
-               primgroup_size = cmd_buffer->state.pipeline->graphics.tess.num_patches;
-       else if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
-               primgroup_size = 64;  /* recommended with a GS */
+       multi_instances_smaller_than_primgroup = indirect_draw;
+       if (!multi_instances_smaller_than_primgroup && instanced_draw) {
+               uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
+               if (num_prims < cmd_buffer->state.pipeline->graphics.primgroup_size)
+                       multi_instances_smaller_than_primgroup = true;
+       }
 
-       multi_instances_smaller_than_primgroup = indirect_draw || (instanced_draw &&
-                                                                  num_prims < primgroup_size);
        if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
                ia_switch_on_eoi = true;
 
@@ -799,7 +797,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
                        ia_switch_on_eoi = true;
 
                /* GS requirement. */
-               if (SI_GS_PER_ES / primgroup_size >= cmd_buffer->device->gs_table_depth - 3)
+               if (SI_GS_PER_ES / cmd_buffer->state.pipeline->graphics.primgroup_size >= cmd_buffer->device->gs_table_depth - 3)
                        partial_es_wave = true;
 
                /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
@@ -808,9 +806,11 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
                 */
                if (family == CHIP_HAWAII && ia_switch_on_eoi) {
                        bool set_vgt_flush = indirect_draw;
-                       if (!set_vgt_flush && instanced_draw)
+                       if (!set_vgt_flush && instanced_draw) {
+                               uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
                                if (num_prims <= 1)
                                        set_vgt_flush = true;
+                       }
                        if (set_vgt_flush)
                                cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
                }
@@ -820,7 +820,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
                S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
                S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
                S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
-               S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
+               S_028AA8_PRIMGROUP_SIZE(cmd_buffer->state.pipeline->graphics.primgroup_size - 1) |
                S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop : 0) |
                /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
                S_028AA8_MAX_PRIMGRP_IN_WAVE(chip_class == VI ?