radv: Initialize DCC on transition from preinitialized.

[mesa.git] / src / amd / vulkan / si_cmd_buffer.c

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 68913ec2ad3caf45318b590372d82f7103877437..f5f4eefcd28373ae23adcb4b4caf52a996f6e362 100644 (file)
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -568,7 +568,8 @@ cik_create_gfx_config(struct radv_device *device)
                                                     cs->cdw * 4, 4096,
                                                     RADEON_DOMAIN_GTT,
                                                     RADEON_FLAG_CPU_ACCESS|
-                                                    RADEON_FLAG_NO_INTERPROCESS_SHARING);
+                                                    RADEON_FLAG_NO_INTERPROCESS_SHARING |
+                                                    RADEON_FLAG_READ_ONLY);
        if (!device->gfx_init)
                goto fail;
 
@@ -673,7 +674,8 @@ si_write_scissors(struct radeon_winsys_cs *cs, int first,
        int i;
        float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
        const float max_range = 32767.0f;
-       assert(count);
+       if (!count)
+               return;
 
        radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
        for (i = 0; i < count; i++) {
@@ -1005,24 +1007,27 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
 #else
                cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
 #endif
-               /* TC    | TC_WB         = invalidate L2 data
-                * TC_MD | TC_WB         = invalidate L2 metadata
-                * TC    | TC_WB | TC_MD = invalidate L2 data & metadata
+               /* These are the only allowed combinations. If you need to
+                * do multiple operations at once, do them separately.
+                * All operations that invalidate L2 also seem to invalidate
+                * metadata. Volatile (VOL) and WC flushes are not listed here.
                 *
-                * The metadata cache must always be invalidated for coherency
-                * between CB/DB and shaders. (metadata = HTILE, CMASK, DCC)
-                *
-                * TC must be invalidated on GFX9 only if the CB/DB surface is
-                * not pipe-aligned. If the surface is RB-aligned, it might not
-                * strictly be pipe-aligned since RB alignment takes precendence.
+                * TC    | TC_WB         = writeback & invalidate L2 & L1
+                * TC    | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
+                *         TC_WB | TC_NC = writeback L2 for MTYPE == NC
+                * TC            | TC_NC = invalidate L2 for MTYPE == NC
+                * TC    | TC_MD         = writeback & invalidate L2 metadata (DCC, etc.)
+                * TCL1                  = invalidate L1
                 */
-               tc_flags = EVENT_TC_WB_ACTION_ENA |
-                          EVENT_TC_MD_ACTION_ENA;
+               tc_flags = EVENT_TC_ACTION_ENA |
+                          EVENT_TC_MD_ACTION_ENA;
 
                /* Ideally flush TC together with CB/DB. */
                if (flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) {
-                       tc_flags |= EVENT_TC_ACTION_ENA |
-                                   EVENT_TCL1_ACTION_ENA;
+                       /* Writeback and invalidate everything in L2 & L1. */
+                       tc_flags = EVENT_TC_ACTION_ENA |
+                                  EVENT_TC_WB_ACTION_ENA;
+
 
                        /* Clear the flags. */
                        flush_bits &= ~(RADV_CMD_FLAG_INV_GLOBAL_L2 |