unsigned num_old_ib_buffers;
unsigned max_num_old_ib_buffers;
unsigned *ib_size_ptr;
- bool failed;
+ VkResult status;
bool is_chained;
int buffer_hash_table[1024];
uint32_t ring;
/**
- * List handle with resources used by this request. This is a raw
- * bo list handle used by the kernel.
+ * BO list handles used by this request.
*/
- uint32_t resources;
+ struct drm_amdgpu_bo_list_entry *handles;
+ uint32_t num_handles;
/**
* Number of dependencies this Command submission needs to
{
struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
- if (cs->failed) {
+ if (cs->status != VK_SUCCESS) {
cs->base.cdw = 0;
return;
}
realloc(cs->old_cs_buffers,
(cs->num_old_cs_buffers + 1) * sizeof(*cs->old_cs_buffers));
if (!cs->old_cs_buffers) {
- cs->failed = true;
+ cs->status = VK_ERROR_OUT_OF_HOST_MEMORY;
cs->base.cdw = 0;
return;
}
if (ib_dws > limit_dws) {
fprintf(stderr, "amdgpu: Too high number of "
"dwords to allocate\n");
- cs->failed = true;
+ cs->status = VK_ERROR_OUT_OF_HOST_MEMORY;
return;
}
}
cs->base.buf = new_buf;
cs->base.max_dw = ib_dws;
} else {
- cs->failed = true;
+ cs->status = VK_ERROR_OUT_OF_HOST_MEMORY;
cs->base.cdw = 0;
}
return;
ib_size = MIN2(ib_size, 0xfffff);
while (!cs->base.cdw || (cs->base.cdw & 7) != 4)
- radeon_emit(&cs->base, 0xffff1000);
+ radeon_emit(&cs->base, PKT3_NOP_PAD);
*cs->ib_size_ptr |= cs->base.cdw + 4;
if (!cs->ib_buffer) {
cs->base.cdw = 0;
- cs->failed = true;
+ cs->status = VK_ERROR_OUT_OF_DEVICE_MEMORY;
cs->ib_buffer = cs->old_ib_buffers[--cs->num_old_ib_buffers];
}
if (!cs->ib_mapped) {
cs->ws->base.buffer_destroy(cs->ib_buffer);
cs->base.cdw = 0;
- cs->failed = true;
+
+ /* VK_ERROR_MEMORY_MAP_FAILED is not valid for vkEndCommandBuffer. */
+ cs->status = VK_ERROR_OUT_OF_DEVICE_MEMORY;
cs->ib_buffer = cs->old_ib_buffers[--cs->num_old_ib_buffers];
}
}
-static bool radv_amdgpu_cs_finalize(struct radeon_cmdbuf *_cs)
+static VkResult radv_amdgpu_cs_finalize(struct radeon_cmdbuf *_cs)
{
struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
if (cs->ws->use_ib_bos) {
while (!cs->base.cdw || (cs->base.cdw & 7) != 0)
- radeon_emit(&cs->base, 0xffff1000);
+ radeon_emit(&cs->base, PKT3_NOP_PAD);
*cs->ib_size_ptr |= cs->base.cdw;
cs->is_chained = false;
}
- return !cs->failed;
+ return cs->status;
}
static void radv_amdgpu_cs_reset(struct radeon_cmdbuf *_cs)
{
struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
cs->base.cdw = 0;
- cs->failed = false;
+ cs->status = VK_SUCCESS;
for (unsigned i = 0; i < cs->num_buffers; ++i) {
unsigned hash = cs->handles[i].bo_handle &
unsigned hash;
int index = radv_amdgpu_cs_find_buffer(cs, bo);
- if (index != -1)
+ if (index != -1 || cs->status != VK_SUCCESS)
return;
if (cs->num_buffers == cs->max_num_buffers) {
unsigned new_count = MAX2(1, cs->max_num_buffers * 2);
- cs->handles = realloc(cs->handles, new_count * sizeof(struct drm_amdgpu_bo_list_entry));
- cs->max_num_buffers = new_count;
+ struct drm_amdgpu_bo_list_entry *new_entries =
+ realloc(cs->handles, new_count * sizeof(struct drm_amdgpu_bo_list_entry));
+ if (new_entries) {
+ cs->max_num_buffers = new_count;
+ cs->handles = new_entries;
+ } else {
+ cs->status = VK_ERROR_OUT_OF_HOST_MEMORY;
+ return;
+ }
}
cs->handles[cs->num_buffers].bo_handle = bo;
}
}
-static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws,
- struct radeon_cmdbuf **cs_array,
- unsigned count,
- struct radv_amdgpu_winsys_bo **extra_bo_array,
- unsigned num_extra_bo,
- struct radeon_cmdbuf *extra_cs,
- const struct radv_winsys_bo_list *radv_bo_list,
- uint32_t *bo_list)
+static VkResult
+radv_amdgpu_get_bo_list(struct radv_amdgpu_winsys *ws,
+ struct radeon_cmdbuf **cs_array,
+ unsigned count,
+ struct radv_amdgpu_winsys_bo **extra_bo_array,
+ unsigned num_extra_bo,
+ struct radeon_cmdbuf *extra_cs,
+ const struct radv_winsys_bo_list *radv_bo_list,
+ unsigned *rnum_handles,
+ struct drm_amdgpu_bo_list_entry **rhandles)
{
- int r = 0;
+ struct drm_amdgpu_bo_list_entry *handles = NULL;
+ unsigned num_handles = 0;
if (ws->debug_all_bos) {
struct radv_amdgpu_winsys_bo *bo;
- struct drm_amdgpu_bo_list_entry *handles;
- unsigned num = 0;
pthread_mutex_lock(&ws->global_bo_list_lock);
handles = malloc(sizeof(handles[0]) * ws->num_buffers);
if (!handles) {
pthread_mutex_unlock(&ws->global_bo_list_lock);
- return -ENOMEM;
+ return VK_ERROR_OUT_OF_HOST_MEMORY;
}
LIST_FOR_EACH_ENTRY(bo, &ws->global_bo_list, global_list_item) {
- assert(num < ws->num_buffers);
- handles[num].bo_handle = bo->bo_handle;
- handles[num].bo_priority = bo->priority;
- num++;
+ assert(num_handles < ws->num_buffers);
+ handles[num_handles].bo_handle = bo->bo_handle;
+ handles[num_handles].bo_priority = bo->priority;
+ num_handles++;
}
- r = amdgpu_bo_list_create_raw(ws->dev, ws->num_buffers,
- handles, bo_list);
- free(handles);
pthread_mutex_unlock(&ws->global_bo_list_lock);
} else if (count == 1 && !num_extra_bo && !extra_cs && !radv_bo_list &&
!radv_amdgpu_cs(cs_array[0])->num_virtual_buffers) {
struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs*)cs_array[0];
- if (cs->num_buffers == 0) {
- *bo_list = 0;
- return 0;
- }
- r = amdgpu_bo_list_create_raw(ws->dev, cs->num_buffers, cs->handles,
- bo_list);
+ if (cs->num_buffers == 0)
+ return VK_SUCCESS;
+
+ handles = malloc(sizeof(handles[0]) * cs->num_buffers);
+ if (!handles)
+ return VK_ERROR_OUT_OF_HOST_MEMORY;
+
+ memcpy(handles, cs->handles,
+ sizeof(handles[0]) * cs->num_buffers);
+ num_handles = cs->num_buffers;
} else {
unsigned total_buffer_count = num_extra_bo;
- unsigned unique_bo_count = num_extra_bo;
+ num_handles = num_extra_bo;
for (unsigned i = 0; i < count; ++i) {
struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs*)cs_array[i];
total_buffer_count += cs->num_buffers;
total_buffer_count += radv_bo_list->count;
}
- if (total_buffer_count == 0) {
- *bo_list = 0;
- return 0;
- }
- struct drm_amdgpu_bo_list_entry *handles = malloc(sizeof(struct drm_amdgpu_bo_list_entry) * total_buffer_count);
+ if (total_buffer_count == 0)
+ return VK_SUCCESS;
+
+ handles = malloc(sizeof(handles[0]) * total_buffer_count);
if (!handles)
- return -ENOMEM;
+ return VK_ERROR_OUT_OF_HOST_MEMORY;
for (unsigned i = 0; i < num_extra_bo; i++) {
handles[i].bo_handle = extra_bo_array[i]->bo_handle;
if (!cs->num_buffers)
continue;
- if (unique_bo_count == 0 && !cs->num_virtual_buffers) {
+ if (num_handles == 0 && !cs->num_virtual_buffers) {
memcpy(handles, cs->handles, cs->num_buffers * sizeof(struct drm_amdgpu_bo_list_entry));
- unique_bo_count = cs->num_buffers;
+ num_handles = cs->num_buffers;
continue;
}
- int unique_bo_so_far = unique_bo_count;
+ int unique_bo_so_far = num_handles;
for (unsigned j = 0; j < cs->num_buffers; ++j) {
bool found = false;
for (unsigned k = 0; k < unique_bo_so_far; ++k) {
}
}
if (!found) {
- handles[unique_bo_count] = cs->handles[j];
- ++unique_bo_count;
+ handles[num_handles] = cs->handles[j];
+ ++num_handles;
}
}
for (unsigned j = 0; j < cs->num_virtual_buffers; ++j) {
for(unsigned k = 0; k < virtual_bo->bo_count; ++k) {
struct radv_amdgpu_winsys_bo *bo = virtual_bo->bos[k];
bool found = false;
- for (unsigned m = 0; m < unique_bo_count; ++m) {
+ for (unsigned m = 0; m < num_handles; ++m) {
if (handles[m].bo_handle == bo->bo_handle) {
found = true;
break;
}
}
if (!found) {
- handles[unique_bo_count].bo_handle = bo->bo_handle;
- handles[unique_bo_count].bo_priority = bo->priority;
- ++unique_bo_count;
+ handles[num_handles].bo_handle = bo->bo_handle;
+ handles[num_handles].bo_priority = bo->priority;
+ ++num_handles;
}
}
}
}
if (radv_bo_list) {
- unsigned unique_bo_so_far = unique_bo_count;
+ unsigned unique_bo_so_far = num_handles;
for (unsigned i = 0; i < radv_bo_list->count; ++i) {
struct radv_amdgpu_winsys_bo *bo = radv_amdgpu_winsys_bo(radv_bo_list->bos[i]);
bool found = false;
}
}
if (!found) {
- handles[unique_bo_count].bo_handle = bo->bo_handle;
- handles[unique_bo_count].bo_priority = bo->priority;
- ++unique_bo_count;
+ handles[num_handles].bo_handle = bo->bo_handle;
+ handles[num_handles].bo_priority = bo->priority;
+ ++num_handles;
}
}
}
-
- if (unique_bo_count > 0) {
- r = amdgpu_bo_list_create_raw(ws->dev, unique_bo_count, handles,
- bo_list);
- } else {
- *bo_list = 0;
- }
-
- free(handles);
}
- return r;
+ *rhandles = handles;
+ *rnum_handles = num_handles;
+
+ return VK_SUCCESS;
}
static struct amdgpu_cs_fence_info radv_set_cs_fence(struct radv_amdgpu_ctx *ctx, int ip_type, int ring)
request);
}
-static int radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx *_ctx,
- int queue_idx,
- struct radv_winsys_sem_info *sem_info,
- const struct radv_winsys_bo_list *radv_bo_list,
- struct radeon_cmdbuf **cs_array,
- unsigned cs_count,
- struct radeon_cmdbuf *initial_preamble_cs,
- struct radeon_cmdbuf *continue_preamble_cs,
- struct radeon_winsys_fence *_fence)
+static VkResult
+radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx *_ctx,
+ int queue_idx,
+ struct radv_winsys_sem_info *sem_info,
+ const struct radv_winsys_bo_list *radv_bo_list,
+ struct radeon_cmdbuf **cs_array,
+ unsigned cs_count,
+ struct radeon_cmdbuf *initial_preamble_cs,
+ struct radeon_cmdbuf *continue_preamble_cs,
+ struct radeon_winsys_fence *_fence)
{
- int r;
struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[0]);
- uint32_t bo_list;
+ struct drm_amdgpu_bo_list_entry *handles = NULL;
struct radv_amdgpu_cs_request request = {0};
struct amdgpu_cs_ib_info ibs[2];
unsigned number_of_ibs = 1;
+ unsigned num_handles = 0;
+ VkResult result;
for (unsigned i = cs_count; i--;) {
struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
}
}
- /* Create a buffer object list. */
- r = radv_amdgpu_create_bo_list(cs0->ws, cs_array, cs_count, NULL, 0,
- initial_preamble_cs, radv_bo_list,
- &bo_list);
- if (r) {
- fprintf(stderr, "amdgpu: buffer list creation failed for the "
- "chained submission(%d)\n", r);
- return r;
- }
+ /* Get the BO list. */
+ result = radv_amdgpu_get_bo_list(cs0->ws, cs_array, cs_count, NULL, 0,
+ initial_preamble_cs, radv_bo_list,
+ &num_handles, &handles);
+ if (result != VK_SUCCESS)
+ return result;
/* Configure the CS request. */
if (initial_preamble_cs) {
request.ring = queue_idx;
request.number_of_ibs = number_of_ibs;
request.ibs = ibs;
- request.resources = bo_list;
+ request.handles = handles;
+ request.num_handles = num_handles;
request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
/* Submit the CS. */
- r = radv_amdgpu_cs_submit(ctx, &request, sem_info);
- if (r) {
- if (r == -ENOMEM)
- fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
- else
- fprintf(stderr, "amdgpu: The CS has been rejected, "
- "see dmesg for more information.\n");
- }
+ result = radv_amdgpu_cs_submit(ctx, &request, sem_info);
- amdgpu_bo_list_destroy_raw(ctx->ws->dev, bo_list);
+ free(request.handles);
- if (r)
- return r;
+ if (result != VK_SUCCESS)
+ return result;
if (fence)
radv_amdgpu_request_to_fence(ctx, fence, &request);
radv_assign_last_submit(ctx, &request);
- return 0;
+ return VK_SUCCESS;
}
-static int radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx *_ctx,
- int queue_idx,
- struct radv_winsys_sem_info *sem_info,
- const struct radv_winsys_bo_list *radv_bo_list,
- struct radeon_cmdbuf **cs_array,
- unsigned cs_count,
- struct radeon_cmdbuf *initial_preamble_cs,
- struct radeon_cmdbuf *continue_preamble_cs,
- struct radeon_winsys_fence *_fence)
+static VkResult
+radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx *_ctx,
+ int queue_idx,
+ struct radv_winsys_sem_info *sem_info,
+ const struct radv_winsys_bo_list *radv_bo_list,
+ struct radeon_cmdbuf **cs_array,
+ unsigned cs_count,
+ struct radeon_cmdbuf *initial_preamble_cs,
+ struct radeon_cmdbuf *continue_preamble_cs,
+ struct radeon_winsys_fence *_fence)
{
- int r;
struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
- uint32_t bo_list;
+ struct drm_amdgpu_bo_list_entry *handles = NULL;
struct radv_amdgpu_cs_request request = {};
struct amdgpu_cs_ib_info *ibs;
struct radv_amdgpu_cs *cs0;
+ unsigned num_handles = 0;
unsigned number_of_ibs;
+ VkResult result;
assert(cs_count);
cs0 = radv_amdgpu_cs(cs_array[0]);
/* Compute the number of IBs for this submit. */
number_of_ibs = cs_count + !!initial_preamble_cs;
- /* Create a buffer object list. */
- r = radv_amdgpu_create_bo_list(cs0->ws, &cs_array[0], cs_count, NULL, 0,
- initial_preamble_cs, radv_bo_list,
- &bo_list);
- if (r) {
- fprintf(stderr, "amdgpu: buffer list creation failed "
- "for the fallback submission (%d)\n", r);
- return r;
- }
+ /* Get the BO list. */
+ result = radv_amdgpu_get_bo_list(cs0->ws, &cs_array[0], cs_count, NULL, 0,
+ initial_preamble_cs, radv_bo_list,
+ &num_handles, &handles);
+ if (result != VK_SUCCESS)
+ return result;
ibs = malloc(number_of_ibs * sizeof(*ibs));
if (!ibs) {
- amdgpu_bo_list_destroy_raw(ctx->ws->dev, bo_list);
- return -ENOMEM;
+ free(request.handles);
+ return VK_ERROR_OUT_OF_HOST_MEMORY;
}
/* Configure the CS request. */
request.ip_type = cs0->hw_ip;
request.ring = queue_idx;
- request.resources = bo_list;
+ request.handles = handles;
+ request.num_handles = num_handles;
request.number_of_ibs = number_of_ibs;
request.ibs = ibs;
request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
/* Submit the CS. */
- r = radv_amdgpu_cs_submit(ctx, &request, sem_info);
- if (r) {
- if (r == -ENOMEM)
- fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
- else
- fprintf(stderr, "amdgpu: The CS has been rejected, "
- "see dmesg for more information.\n");
- }
+ result = radv_amdgpu_cs_submit(ctx, &request, sem_info);
- amdgpu_bo_list_destroy_raw(ctx->ws->dev, bo_list);
+ free(request.handles);
free(ibs);
- if (r)
- return r;
+ if (result != VK_SUCCESS)
+ return result;
if (fence)
radv_amdgpu_request_to_fence(ctx, fence, &request);
radv_assign_last_submit(ctx, &request);
- return 0;
+ return VK_SUCCESS;
}
-static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
- int queue_idx,
- struct radv_winsys_sem_info *sem_info,
- const struct radv_winsys_bo_list *radv_bo_list,
- struct radeon_cmdbuf **cs_array,
- unsigned cs_count,
- struct radeon_cmdbuf *initial_preamble_cs,
- struct radeon_cmdbuf *continue_preamble_cs,
- struct radeon_winsys_fence *_fence)
+static VkResult
+radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
+ int queue_idx,
+ struct radv_winsys_sem_info *sem_info,
+ const struct radv_winsys_bo_list *radv_bo_list,
+ struct radeon_cmdbuf **cs_array,
+ unsigned cs_count,
+ struct radeon_cmdbuf *initial_preamble_cs,
+ struct radeon_cmdbuf *continue_preamble_cs,
+ struct radeon_winsys_fence *_fence)
{
- int r;
struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[0]);
struct radeon_winsys *ws = (struct radeon_winsys*)cs0->ws;
- uint32_t bo_list;
struct radv_amdgpu_cs_request request;
- uint32_t pad_word = 0xffff1000U;
+ uint32_t pad_word = PKT3_NOP_PAD;
bool emit_signal_sem = sem_info->cs_emit_signal;
+ VkResult result;
if (radv_amdgpu_winsys(ws)->info.chip_class == GFX6)
pad_word = 0x80000000;
struct radeon_winsys_bo **bos;
struct radeon_cmdbuf *preamble_cs = i ? continue_preamble_cs : initial_preamble_cs;
struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
+ struct drm_amdgpu_bo_list_entry *handles = NULL;
+ unsigned num_handles = 0;
unsigned number_of_ibs;
uint32_t *ptr;
unsigned cnt = 0;
ibs = malloc(number_of_ibs * sizeof(*ibs));
if (!ibs)
- return -ENOMEM;
+ return VK_ERROR_OUT_OF_HOST_MEMORY;
bos = malloc(number_of_ibs * sizeof(*bos));
if (!bos) {
free(ibs);
- return -ENOMEM;
+ return VK_ERROR_OUT_OF_HOST_MEMORY;
}
if (number_of_ibs > 1) {
ibs[0].flags = 0;
}
- r = radv_amdgpu_create_bo_list(cs0->ws, &cs_array[i], cnt,
- (struct radv_amdgpu_winsys_bo **)bos,
- number_of_ibs, preamble_cs,
- radv_bo_list, &bo_list);
- if (r) {
- fprintf(stderr, "amdgpu: buffer list creation failed "
- "for the sysmem submission (%d)\n", r);
+ result = radv_amdgpu_get_bo_list(cs0->ws, &cs_array[i], cnt,
+ (struct radv_amdgpu_winsys_bo **)bos,
+ number_of_ibs, preamble_cs,
+ radv_bo_list,
+ &num_handles, &handles);
+ if (result != VK_SUCCESS) {
free(ibs);
free(bos);
- return r;
+ return result;
}
memset(&request, 0, sizeof(request));
request.ip_type = cs0->hw_ip;
request.ring = queue_idx;
- request.resources = bo_list;
+ request.handles = handles;
+ request.num_handles = num_handles;
request.number_of_ibs = number_of_ibs;
request.ibs = ibs;
request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
sem_info->cs_emit_signal = (i == cs_count - cnt) ? emit_signal_sem : false;
- r = radv_amdgpu_cs_submit(ctx, &request, sem_info);
- if (r) {
- if (r == -ENOMEM)
- fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
- else
- fprintf(stderr, "amdgpu: The CS has been rejected, "
- "see dmesg for more information.\n");
- }
+ result = radv_amdgpu_cs_submit(ctx, &request, sem_info);
- amdgpu_bo_list_destroy_raw(ctx->ws->dev, bo_list);
+ free(request.handles);
for (unsigned j = 0; j < number_of_ibs; j++) {
ws->buffer_destroy(bos[j]);
free(ibs);
free(bos);
- if (r)
- return r;
+ if (result != VK_SUCCESS)
+ return result;
i += cnt;
}
radv_assign_last_submit(ctx, &request);
- return 0;
+ return VK_SUCCESS;
}
-static int radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx *_ctx,
- int queue_idx,
- struct radeon_cmdbuf **cs_array,
- unsigned cs_count,
- struct radeon_cmdbuf *initial_preamble_cs,
- struct radeon_cmdbuf *continue_preamble_cs,
- struct radv_winsys_sem_info *sem_info,
- const struct radv_winsys_bo_list *bo_list,
- bool can_patch,
- struct radeon_winsys_fence *_fence)
+static VkResult radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx *_ctx,
+ int queue_idx,
+ struct radeon_cmdbuf **cs_array,
+ unsigned cs_count,
+ struct radeon_cmdbuf *initial_preamble_cs,
+ struct radeon_cmdbuf *continue_preamble_cs,
+ struct radv_winsys_sem_info *sem_info,
+ const struct radv_winsys_bo_list *bo_list,
+ bool can_patch,
+ struct radeon_winsys_fence *_fence)
{
struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[0]);
struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
- int ret;
+ VkResult result;
assert(sem_info);
if (!cs->ws->use_ib_bos) {
- ret = radv_amdgpu_winsys_cs_submit_sysmem(_ctx, queue_idx, sem_info, bo_list, cs_array,
- cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
+ result = radv_amdgpu_winsys_cs_submit_sysmem(_ctx, queue_idx, sem_info, bo_list, cs_array,
+ cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
} else if (can_patch) {
- ret = radv_amdgpu_winsys_cs_submit_chained(_ctx, queue_idx, sem_info, bo_list, cs_array,
- cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
+ result = radv_amdgpu_winsys_cs_submit_chained(_ctx, queue_idx, sem_info, bo_list, cs_array,
+ cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
} else {
- ret = radv_amdgpu_winsys_cs_submit_fallback(_ctx, queue_idx, sem_info, bo_list, cs_array,
- cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
+ result = radv_amdgpu_winsys_cs_submit_fallback(_ctx, queue_idx, sem_info, bo_list, cs_array,
+ cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
}
radv_amdgpu_signal_sems(ctx, cs->hw_ip, queue_idx, sem_info);
- return ret;
+ return result;
}
static void *radv_amdgpu_winsys_get_cpu_addr(void *_cs, uint64_t addr)
return syncobj;
}
-static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx,
- struct radv_amdgpu_cs_request *request,
- struct radv_winsys_sem_info *sem_info)
+static VkResult
+radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx,
+ struct radv_amdgpu_cs_request *request,
+ struct radv_winsys_sem_info *sem_info)
{
int r;
int num_chunks;
struct drm_amdgpu_cs_chunk_data *chunk_data;
struct drm_amdgpu_cs_chunk_dep *sem_dependencies = NULL;
struct drm_amdgpu_cs_chunk_sem *wait_syncobj = NULL, *signal_syncobj = NULL;
+ bool use_bo_list_create = ctx->ws->info.drm_minor < 27;
+ struct drm_amdgpu_bo_list_in bo_list_in;
int i;
struct amdgpu_cs_fence *sem;
+ uint32_t bo_list = 0;
+ VkResult result = VK_SUCCESS;
user_fence = (request->fence_info.handle != NULL);
- size = request->number_of_ibs + (user_fence ? 2 : 1) + 3;
+ size = request->number_of_ibs + (user_fence ? 2 : 1) + (!use_bo_list_create ? 1 : 0) + 3;
- chunks = alloca(sizeof(struct drm_amdgpu_cs_chunk) * size);
+ chunks = malloc(sizeof(chunks[0]) * size);
+ if (!chunks)
+ return VK_ERROR_OUT_OF_HOST_MEMORY;
size = request->number_of_ibs + (user_fence ? 1 : 0);
- chunk_data = alloca(sizeof(struct drm_amdgpu_cs_chunk_data) * size);
+ chunk_data = malloc(sizeof(chunk_data[0]) * size);
+ if (!chunk_data) {
+ result = VK_ERROR_OUT_OF_HOST_MEMORY;
+ goto error_out;
+ }
num_chunks = request->number_of_ibs;
for (i = 0; i < request->number_of_ibs; i++) {
&chunks[num_chunks],
AMDGPU_CHUNK_ID_SYNCOBJ_IN);
if (!wait_syncobj) {
- r = -ENOMEM;
+ result = VK_ERROR_OUT_OF_HOST_MEMORY;
goto error_out;
}
num_chunks++;
}
if (sem_info->wait.sem_count && sem_info->cs_emit_wait) {
- sem_dependencies = alloca(sizeof(struct drm_amdgpu_cs_chunk_dep) * sem_info->wait.sem_count);
+ sem_dependencies = malloc(sizeof(sem_dependencies[0]) * sem_info->wait.sem_count);
+ if (!sem_dependencies) {
+ result = VK_ERROR_OUT_OF_HOST_MEMORY;
+ goto error_out;
+ }
+
int sem_count = 0;
for (unsigned j = 0; j < sem_info->wait.sem_count; j++) {
&chunks[num_chunks],
AMDGPU_CHUNK_ID_SYNCOBJ_OUT);
if (!signal_syncobj) {
- r = -ENOMEM;
+ result = VK_ERROR_OUT_OF_HOST_MEMORY;
goto error_out;
}
num_chunks++;
}
+ if (use_bo_list_create) {
+ /* Legacy path creating the buffer list handle and passing it
+ * to the CS ioctl.
+ */
+ r = amdgpu_bo_list_create_raw(ctx->ws->dev, request->num_handles,
+ request->handles, &bo_list);
+ if (r) {
+ if (r == -ENOMEM) {
+ fprintf(stderr, "amdgpu: Not enough memory for buffer list creation.\n");
+ result = VK_ERROR_OUT_OF_HOST_MEMORY;
+ } else {
+ fprintf(stderr, "amdgpu: buffer list creation failed (%d).\n", r);
+ result = VK_ERROR_UNKNOWN;
+ }
+ goto error_out;
+ }
+ } else {
+ /* Standard path passing the buffer list via the CS ioctl. */
+ bo_list_in.operation = ~0;
+ bo_list_in.list_handle = ~0;
+ bo_list_in.bo_number = request->num_handles;
+ bo_list_in.bo_info_size = sizeof(struct drm_amdgpu_bo_list_entry);
+ bo_list_in.bo_info_ptr = (uint64_t)(uintptr_t)request->handles;
+
+ chunks[num_chunks].chunk_id = AMDGPU_CHUNK_ID_BO_HANDLES;
+ chunks[num_chunks].length_dw = sizeof(struct drm_amdgpu_bo_list_in) / 4;
+ chunks[num_chunks].chunk_data = (uintptr_t)&bo_list_in;
+ num_chunks++;
+ }
+
r = amdgpu_cs_submit_raw2(ctx->ws->dev,
ctx->ctx,
- request->resources,
+ bo_list,
num_chunks,
chunks,
&request->seq_no);
+
+ if (bo_list)
+ amdgpu_bo_list_destroy_raw(ctx->ws->dev, bo_list);
+
+ if (r) {
+ if (r == -ENOMEM) {
+ fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
+ result = VK_ERROR_OUT_OF_HOST_MEMORY;
+ } else if (r == -ECANCELED) {
+ fprintf(stderr, "amdgpu: The CS has been cancelled because the context is lost.\n");
+ result = VK_ERROR_DEVICE_LOST;
+ } else {
+ fprintf(stderr, "amdgpu: The CS has been rejected, "
+ "see dmesg for more information (%i).\n", r);
+ result = VK_ERROR_UNKNOWN;
+ }
+ }
+
error_out:
+ free(chunks);
+ free(chunk_data);
+ free(sem_dependencies);
free(wait_syncobj);
free(signal_syncobj);
- return r;
+ return result;
}
static int radv_amdgpu_create_syncobj(struct radeon_winsys *_ws,
+ bool create_signaled,
uint32_t *handle)
{
struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
- return amdgpu_cs_create_syncobj(ws->dev, handle);
+ uint32_t flags = 0;
+
+ if (create_signaled)
+ flags |= DRM_SYNCOBJ_CREATE_SIGNALED;
+
+ return amdgpu_cs_create_syncobj2(ws->dev, flags, handle);
}
static void radv_amdgpu_destroy_syncobj(struct radeon_winsys *_ws,
projects / mesa.git / blobdiff