ISA: Set up common trace flags for tracing registers.

[gem5.git] / src / arch / SConscript

diff --git a/src/arch/SConscript b/src/arch/SConscript
index e051c44af6802cf6f25c3e8619a7e35cfc33fd71..2b0af2816b8772d9014caa65ff3b860739bc98b8 100644 (file)
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -49,6 +49,7 @@ isa_switch_hdrs = Split('''
         isa_traits.hh
         kernel_stats.hh
         locked_mem.hh
+        microcode_rom.hh
         mmaped_ipr.hh
         process.hh
         predecoder.hh
@@ -97,7 +98,7 @@ execfile(cpu_models_file.srcnode().abspath)
 
 # Several files are generated from the ISA description.
 # We always get the basic decoder and header file.
-isa_desc_gen_files = [ 'decoder.cc', 'decoder.hh' ]
+isa_desc_gen_files = [ 'decoder.cc', 'decoder.hh', 'max_inst_regs.hh' ]
 # We also get an execute file for each selected CPU model.
 isa_desc_gen_files += [CpuModel.dict[cpu].filename
                        for cpu in env['CPU_MODELS']]
@@ -125,3 +126,8 @@ else:
                                emitter = isa_desc_emitter)
 
 env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
+
+TraceFlag('IntRegs')
+TraceFlag('FloatRegs')
+TraceFlag('MiscRegs')
+CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ])