ARM: Fix type comparison warnings in Neon.

[gem5.git] / src / arch / SConscript

diff --git a/src/arch/SConscript b/src/arch/SConscript
index a67cf869a7c65ea4ecbd2f90384ad7a9317af4f7..9ebc6986bf1ba9526524af4f577bc917f9618c2e 100644 (file)
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -43,7 +43,6 @@ Import('*')
 
 # List of headers to generate
 isa_switch_hdrs = Split('''
-        arguments.hh
         faults.hh
         interrupts.hh
        isa.hh
@@ -55,7 +54,7 @@ isa_switch_hdrs = Split('''
         mt.hh
         process.hh
         predecoder.hh
-        regfile.hh
+        registers.hh
         remote_gdb.hh
         stacktrace.hh
         tlb.hh
@@ -90,41 +89,39 @@ env.Append(SCANNERS = isa_scanner)
 # output from the ISA description (*.isa) files.
 #
 
-# Convert to File node to fix path
-isa_parser = File('isa_parser.py')
-cpu_models_file = File('../cpu/cpu_models.py')
+# The emitter patches up the sources & targets to include the
+# autogenerated files as targets and isa parser itself as a source.
+def isa_desc_emitter(target, source, env):
+    cpu_models = list(env['CPU_MODELS'])
+    if env['USE_CHECKER']:
+        cpu_models.append('CheckerCPU')
 
-# This sucks in the defintions of the CpuModel objects.
-execfile(cpu_models_file.srcnode().abspath)
+    # Several files are generated from the ISA description.
+    # We always get the basic decoder and header file.
+    target = [ 'decoder.cc', 'decoder.hh', 'max_inst_regs.hh' ]
+    # We also get an execute file for each selected CPU model.
+    target += [CpuModel.dict[cpu].filename for cpu in cpu_models]
 
-# Several files are generated from the ISA description.
-# We always get the basic decoder and header file.
-isa_desc_gen_files = [ 'decoder.cc', 'decoder.hh', 'max_inst_regs.hh' ]
-# We also get an execute file for each selected CPU model.
-isa_desc_gen_files += [CpuModel.dict[cpu].filename
-                       for cpu in env['CPU_MODELS']]
+    return target, source + [ Value(m) for m in cpu_models ]
 
-# Also include the CheckerCPU as one of the models if it is being
-# enabled via command line.
-if env['USE_CHECKER']:
-    isa_desc_gen_files += [CpuModel.dict['CheckerCPU'].filename]
+ARCH_DIR = Dir('.')
 
-# The emitter patches up the sources & targets to include the
-# autogenerated files as targets and isa parser itself as a source.
-def isa_desc_emitter(target, source, env):
-    return (isa_desc_gen_files, [isa_parser, cpu_models_file] + source)
+# import ply here because SCons screws with sys.path when performing actions.
+import ply
+
+def isa_desc_action(target, source, env):
+    # Add the current directory to the system path so we can import files
+    sys.path[0:0] = [ ARCH_DIR.srcnode().abspath ]
+    import isa_parser
 
-# Pieces are in place, so create the builder.
-python = sys.executable  # use same Python binary used to run scons
+    models = [ s.get_contents() for s in source[1:] ]
+    cpu_models = [CpuModel.dict[cpu] for cpu in models]
+    parser = isa_parser.ISAParser(target[0].dir.abspath, cpu_models)
+    parser.parse_isa_desc(source[0].abspath)
 
 # Also include the CheckerCPU as one of the models if it is being
 # enabled via command line.
-if env['USE_CHECKER']:
-    isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS CheckerCPU',
-                               emitter = isa_desc_emitter)
-else:
-    isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS',
-                               emitter = isa_desc_emitter)
+isa_desc_builder = Builder(action=isa_desc_action, emitter=isa_desc_emitter)
 
 env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })