DMA: Split the DMA device and IO device into seperate files

[gem5.git] / src / arch / SConscript

diff --git a/src/arch/SConscript b/src/arch/SConscript
index 61b57031360236437e3e35e1e4c3b505d9c972dc..d423fe9ead60e3c62224afe48658dfea27a7cfe8 100644 (file)
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -29,6 +29,7 @@
 # Authors: Steve Reinhardt
 
 import sys
+import os
 
 Import('*')
 
@@ -43,15 +44,13 @@ Import('*')
 
 # List of headers to generate
 isa_switch_hdrs = Split('''
-        arguments.hh
-        faults.hh
         interrupts.hh
-       isa.hh
+        isa.hh
         isa_traits.hh
         kernel_stats.hh
         locked_mem.hh
         microcode_rom.hh
-        mmaped_ipr.hh
+        mmapped_ipr.hh
         mt.hh
         process.hh
         predecoder.hh
@@ -90,22 +89,13 @@ env.Append(SCANNERS = isa_scanner)
 # output from the ISA description (*.isa) files.
 #
 
-#
-# Grab the CPU Model information
-#
-
-# Convert to File node to fix path
-cpu_models_file = File('../cpu/cpu_models.py')
-
-# This sucks in the defintions of the CpuModel objects.
-execfile(cpu_models_file.srcnode().abspath)
+isa_parser = File('isa_parser.py')
 
 # The emitter patches up the sources & targets to include the
 # autogenerated files as targets and isa parser itself as a source.
 def isa_desc_emitter(target, source, env):
     cpu_models = list(env['CPU_MODELS'])
-    if env['USE_CHECKER']:
-        cpu_models.append('CheckerCPU')
+    cpu_models.append('CheckerCPU')
 
     # Several files are generated from the ISA description.
     # We always get the basic decoder and header file.
@@ -113,19 +103,29 @@ def isa_desc_emitter(target, source, env):
     # We also get an execute file for each selected CPU model.
     target += [CpuModel.dict[cpu].filename for cpu in cpu_models]
 
-    return target, source + [ Value(m) for m in cpu_models ]
+    # List the isa parser as a source.
+    source += [ isa_parser ]
+    # Add in the CPU models.
+    source += [ Value(m) for m in cpu_models ]
+
+    return [os.path.join("generated", t) for t in target], source
 
 ARCH_DIR = Dir('.')
 
-def isa_desc_action(target, source, env):
+# import ply here because SCons screws with sys.path when performing actions.
+import ply
+
+def isa_desc_action_func(target, source, env):
     # Add the current directory to the system path so we can import files
     sys.path[0:0] = [ ARCH_DIR.srcnode().abspath ]
     import isa_parser
 
-    models = [ s.get_contents() for s in source[1:] ]
+    # Skip over the ISA description itself and the parser to the CPU models.
+    models = [ s.get_contents() for s in source[2:] ]
     cpu_models = [CpuModel.dict[cpu] for cpu in models]
     parser = isa_parser.ISAParser(target[0].dir.abspath, cpu_models)
     parser.parse_isa_desc(source[0].abspath)
+isa_desc_action = MakeAction(isa_desc_action_func, Transform("ISA DESC", 1))
 
 # Also include the CheckerCPU as one of the models if it is being
 # enabled via command line.
@@ -133,7 +133,7 @@ isa_desc_builder = Builder(action=isa_desc_action, emitter=isa_desc_emitter)
 
 env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
 
-TraceFlag('IntRegs')
-TraceFlag('FloatRegs')
-TraceFlag('MiscRegs')
+DebugFlag('IntRegs')
+DebugFlag('FloatRegs')
+DebugFlag('MiscRegs')
 CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ])