ISA: Make the decode function part of the ISA's decoder.

[gem5.git] / src / arch / SConscript

diff --git a/src/arch/SConscript b/src/arch/SConscript
index 66f93870e75aa22b0e734a2744d95c5d1db12e4a..f271f487f5904c169c424efd6aa71792bca95111 100644 (file)
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -29,6 +29,7 @@
 # Authors: Steve Reinhardt
 
 import sys
+import os
 
 Import('*')
 
@@ -43,19 +44,20 @@ Import('*')
 
 # List of headers to generate
 isa_switch_hdrs = Split('''
-        arguments.hh
-        faults.hh
+        decoder.hh
         interrupts.hh
+        isa.hh
         isa_traits.hh
         kernel_stats.hh
         locked_mem.hh
-        mmaped_ipr.hh
+        microcode_rom.hh
+        mmapped_ipr.hh
+        mt.hh
         process.hh
         predecoder.hh
-        regfile.hh
+        registers.hh
         remote_gdb.hh
         stacktrace.hh
-        syscallreturn.hh
         tlb.hh
         types.hh
         utility.hh
@@ -88,40 +90,51 @@ env.Append(SCANNERS = isa_scanner)
 # output from the ISA description (*.isa) files.
 #
 
-# Convert to File node to fix path
 isa_parser = File('isa_parser.py')
-cpu_models_file = File('../cpu/cpu_models.py')
-
-# This sucks in the defintions of the CpuModel objects.
-execfile(cpu_models_file.srcnode().abspath)
-
-# Several files are generated from the ISA description.
-# We always get the basic decoder and header file.
-isa_desc_gen_files = [ 'decoder.cc', 'decoder.hh', 'max_inst_regs.hh' ]
-# We also get an execute file for each selected CPU model.
-isa_desc_gen_files += [CpuModel.dict[cpu].filename
-                       for cpu in env['CPU_MODELS']]
-
-# Also include the CheckerCPU as one of the models if it is being
-# enabled via command line.
-if env['USE_CHECKER']:
-    isa_desc_gen_files += [CpuModel.dict['CheckerCPU'].filename]
 
 # The emitter patches up the sources & targets to include the
 # autogenerated files as targets and isa parser itself as a source.
 def isa_desc_emitter(target, source, env):
-    return (isa_desc_gen_files, [isa_parser, cpu_models_file] + source)
+    cpu_models = list(env['CPU_MODELS'])
+    cpu_models.append('CheckerCPU')
+
+    # Several files are generated from the ISA description.
+    # We always get the basic decoder and header file.
+    target = [ 'decoder.cc', 'decoder.hh', 'max_inst_regs.hh' ]
+    # We also get an execute file for each selected CPU model.
+    target += [CpuModel.dict[cpu].filename for cpu in cpu_models]
 
-# Pieces are in place, so create the builder.
-python = sys.executable  # use same Python binary used to run scons
+    # List the isa parser as a source.
+    source += [ isa_parser ]
+    # Add in the CPU models.
+    source += [ Value(m) for m in cpu_models ]
+
+    return [os.path.join("generated", t) for t in target], source
+
+ARCH_DIR = Dir('.')
+
+# import ply here because SCons screws with sys.path when performing actions.
+import ply
+
+def isa_desc_action_func(target, source, env):
+    # Add the current directory to the system path so we can import files
+    sys.path[0:0] = [ ARCH_DIR.srcnode().abspath ]
+    import isa_parser
+
+    # Skip over the ISA description itself and the parser to the CPU models.
+    models = [ s.get_contents() for s in source[2:] ]
+    cpu_models = [CpuModel.dict[cpu] for cpu in models]
+    parser = isa_parser.ISAParser(target[0].dir.abspath, cpu_models)
+    parser.parse_isa_desc(source[0].abspath)
+isa_desc_action = MakeAction(isa_desc_action_func, Transform("ISA DESC", 1))
 
 # Also include the CheckerCPU as one of the models if it is being
 # enabled via command line.
-if env['USE_CHECKER']:
-    isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS CheckerCPU',
-                               emitter = isa_desc_emitter)
-else:
-    isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS',
-                               emitter = isa_desc_emitter)
+isa_desc_builder = Builder(action=isa_desc_action, emitter=isa_desc_emitter)
 
 env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
+
+DebugFlag('IntRegs')
+DebugFlag('FloatRegs')
+DebugFlag('MiscRegs')
+CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ])