X86: Define a noop ExtMachInst.

[gem5.git] / src / arch / alpha / ev5.cc

diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 166d42bc6c74da3d916d6a0cab637d9dcd38ab41..609b45957f8339d768694b6661bf5c4a218bef70 100644 (file)
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -34,14 +34,12 @@
 #include "arch/alpha/kernel_stats.hh"
 #include "arch/alpha/osfpal.hh"
 #include "arch/alpha/tlb.hh"
-#include "arch/alpha/kgdb.h"
-#include "base/remote_gdb.hh"
-#include "base/stats/events.hh"
+#include "base/cp_annotate.hh"
+#include "base/debug.hh"
 #include "config/full_system.hh"
 #include "cpu/base.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/thread_context.hh"
-#include "sim/debug.hh"
 #include "sim/sim_exit.hh"
 
 namespace AlphaISA {
@@ -126,18 +124,6 @@ zeroRegisters(CPU *cpu)
     cpu->thread->setFloatReg(ZeroReg, 0.0);
 }
 
-int
-MiscRegFile::getInstAsid()
-{
-    return ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
-}
-
-int
-MiscRegFile::getDataAsid()
-{
-    return DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
-}
-
 #endif
 
 ////////////////////////////////////////////////////////////////////////
@@ -157,7 +143,7 @@ initIPRs(ThreadContext *tc, int cpuId)
 }
 
 MiscReg
-MiscRegFile::readIpr(int idx, ThreadContext *tc)
+ISA::readIpr(int idx, ThreadContext *tc)
 {
     uint64_t retval = 0;        // return value, default 0
 
@@ -269,7 +255,7 @@ int break_ipl = -1;
 #endif
 
 void
-MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
+ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
 {
     uint64_t old;
 
@@ -350,7 +336,7 @@ MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
 
       case IPR_IPLR:
 #ifdef DEBUG
-        if (break_ipl != -1 && break_ipl == (val & 0x1f))
+        if (break_ipl != -1 && break_ipl == (int)(val & 0x1f))
             debug_break();
 #endif
 
@@ -459,8 +445,7 @@ MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
         // really a control write
         ipr[idx] = val;
 
-        tc->getDTBPtr()->flushAddr(val,
-                DTB_ASN_ASN(ipr[IPR_DTB_ASN]));
+        tc->getDTBPtr()->flushAddr(val, DTB_ASN_ASN(ipr[IPR_DTB_ASN]));
         break;
 
       case IPR_DTB_TAG: {
@@ -529,8 +514,7 @@ MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
         // really a control write
         ipr[idx] = val;
 
-        tc->getITBPtr()->flushAddr(val,
-                ITB_ASN_ASN(ipr[IPR_ITB_ASN]));
+        tc->getITBPtr()->flushAddr(val, ITB_ASN_ASN(ipr[IPR_ITB_ASN]));
         break;
 
       default:
@@ -541,18 +525,17 @@ MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
     // no error...
 }
 
-
 void
 copyIprs(ThreadContext *src, ThreadContext *dest)
 {
-    for (int i = 0; i < NumInternalProcRegs; ++i) {
+    for (int i = 0; i < NumInternalProcRegs; ++i)
         dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
-    }
 }
 
 } // namespace AlphaISA
 
 #if FULL_SYSTEM
+
 using namespace AlphaISA;
 
 Fault
@@ -563,6 +546,8 @@ SimpleThread::hwrei()
 
     setNextPC(readMiscRegNoEffect(IPR_EXC_ADDR));
 
+    CPA::cpa()->swAutoBegin(tc, readNextPC());
+
     if (!misspeculating()) {
         if (kernelStats)
             kernelStats->hwrei();