ARM: Decode neon memory instructions.

[gem5.git] / src / arch / alpha / ev5.hh

diff --git a/src/arch/alpha/ev5.hh b/src/arch/alpha/ev5.hh
index a40ca6749ebecde813278991a4828e58e9913ae3..5abc7e57f16692f811330c0859da14c8d448a39a 100644 (file)
--- a/src/arch/alpha/ev5.hh
+++ b/src/arch/alpha/ev5.hh
@@ -33,17 +33,13 @@
 #ifndef __ARCH_ALPHA_EV5_HH__
 #define __ARCH_ALPHA_EV5_HH__
 
-#include "config/alpha_tlaser.hh"
 #include "arch/alpha/isa_traits.hh"
 
+class ThreadContext;
+
 namespace AlphaISA {
 
-#if ALPHA_TLASER
-const uint64_t AsnMask = ULL(0x7f);
-#else
 const uint64_t AsnMask = ULL(0xff);
-#endif
-
 const int VAddrImplBits = 43;
 const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1;
 const Addr VAddrUnImplMask = ~VAddrImplMask;
@@ -53,32 +49,27 @@ inline Addr VAddrOffset(Addr a) { return a & PageOffset; }
 inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; }
 inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; }
 
-#if ALPHA_TLASER
-inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); }
-const int PAddrImplBits = 40;
-#else
 inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); }
 const int PAddrImplBits = 44; // for Tsunami
-#endif
 const Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1;
 const Addr PAddrUncachedBit39 = ULL(0x8000000000);
 const Addr PAddrUncachedBit40 = ULL(0x10000000000);
 const Addr PAddrUncachedBit43 = ULL(0x80000000000);
 const Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35>
-inline Addr Phys2K0Seg(Addr addr)
+
+inline Addr
+Phys2K0Seg(Addr addr)
 {
-#if !ALPHA_TLASER
     if (addr & PAddrUncachedBit43) {
         addr &= PAddrUncachedMask;
         addr |= PAddrUncachedBit40;
     }
-#endif
     return addr | K0SegBase;
 }
 
 inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; }
 inline Addr DTB_PTE_PPN(uint64_t reg)
-{ return reg >> 32 & (ULL(1) << PAddrImplBits - PageShift) - 1; }
+{ return reg >> 32 & ((ULL(1) << (PAddrImplBits - PageShift)) - 1); }
 inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
 inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; }
 inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
@@ -88,7 +79,7 @@ inline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
 
 inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; }
 inline Addr ITB_PTE_PPN(uint64_t reg)
-{ return reg >> 32 & (ULL(1) << PAddrImplBits - PageShift) - 1; }
+{ return reg >> 32 & ((ULL(1) << (PAddrImplBits - PageShift)) - 1); }
 inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
 inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
 inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
@@ -117,6 +108,8 @@ inline int Ra(MachInst inst) { return inst >> 21 & 0x1f; }
 const Addr PalBase = 0x4000;
 const Addr PalMax = 0x10000;
 
+void copyIprs(ThreadContext *src, ThreadContext *dest);
+
 } // namespace AlphaISA
 
 #endif // __ARCH_ALPHA_EV5_HH__