mem: update stuff for changes to Packet and Request

[gem5.git] / src / arch / alpha / faults.cc

diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index 7d4de902a5b4ba7e9c66f7e7350d17fa61a75c05..e89cf5c6405ee3b4331db2aedd8887246b2dbf5d 100644 (file)
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -40,8 +40,7 @@
 #include "mem/page_table.hh"
 #endif
 
-namespace AlphaISA
-{
+namespace AlphaISA {
 
 FaultName MachineCheckFault::_name = "mchk";
 FaultVect MachineCheckFault::_vect = 0x0401;
@@ -109,64 +108,67 @@ FaultStat IntegerOverflowFault::_count;
 
 #if FULL_SYSTEM
 
-void AlphaFault::invoke(ThreadContext * tc)
+void
+AlphaFault::invoke(ThreadContext *tc)
 {
     FaultBase::invoke(tc);
     countStat()++;
 
     // exception restart address
     if (setRestartAddress() || !(tc->readPC() & 0x3))
-        tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, tc->readPC());
+        tc->setMiscRegNoEffect(IPR_EXC_ADDR, tc->readPC());
 
     if (skipFaultingInstruction()) {
         // traps...  skip faulting instruction.
-        tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
-                   tc->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR) + 4);
+        tc->setMiscRegNoEffect(IPR_EXC_ADDR,
+                   tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4);
     }
 
-    tc->setPC(tc->readMiscRegNoEffect(AlphaISA::IPR_PAL_BASE) + vect());
+    tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect());
     tc->setNextPC(tc->readPC() + sizeof(MachInst));
 }
 
-void ArithmeticFault::invoke(ThreadContext * tc)
+void
+ArithmeticFault::invoke(ThreadContext *tc)
 {
     FaultBase::invoke(tc);
     panic("Arithmetic traps are unimplemented!");
 }
 
-void DtbFault::invoke(ThreadContext * tc)
+void
+DtbFault::invoke(ThreadContext *tc)
 {
     // Set fault address and flags.  Even though we're modeling an
     // EV5, we use the EV6 technique of not latching fault registers
     // on VPTE loads (instead of locking the registers until IPR_VA is
     // read, like the EV5).  The EV6 approach is cleaner and seems to
     // work with EV5 PAL code, but not the other way around.
-    if (!tc->misspeculating()
-        && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
+    if (!tc->misspeculating() &&
+        reqFlags.none(Request::VPTE|Request::NO_FAULT)) {
         // set VA register with faulting address
-        tc->setMiscRegNoEffect(AlphaISA::IPR_VA, vaddr);
+        tc->setMiscRegNoEffect(IPR_VA, vaddr);
 
         // set MM_STAT register flags
-        tc->setMiscRegNoEffect(AlphaISA::IPR_MM_STAT,
-            (((EV5::Opcode(tc->getInst()) & 0x3f) << 11)
-             | ((EV5::Ra(tc->getInst()) & 0x1f) << 6)
-             | (flags & 0x3f)));
+        tc->setMiscRegNoEffect(IPR_MM_STAT,
+            (((Opcode(tc->getInst()) & 0x3f) << 11) |
+             ((Ra(tc->getInst()) & 0x1f) << 6) |
+             (flags & 0x3f)));
 
         // set VA_FORM register with faulting formatted address
-        tc->setMiscRegNoEffect(AlphaISA::IPR_VA_FORM,
-            tc->readMiscRegNoEffect(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
+        tc->setMiscRegNoEffect(IPR_VA_FORM,
+            tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
     }
 
     AlphaFault::invoke(tc);
 }
 
-void ItbFault::invoke(ThreadContext * tc)
+void
+ItbFault::invoke(ThreadContext *tc)
 {
     if (!tc->misspeculating()) {
-        tc->setMiscRegNoEffect(AlphaISA::IPR_ITB_TAG, pc);
-        tc->setMiscRegNoEffect(AlphaISA::IPR_IFAULT_VA_FORM,
-                       tc->readMiscRegNoEffect(AlphaISA::IPR_IVPTBR) |
-                       (AlphaISA::VAddr(pc).vpn() << 3));
+        tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
+        tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
+            tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
     }
 
     AlphaFault::invoke(tc);
@@ -174,57 +176,33 @@ void ItbFault::invoke(ThreadContext * tc)
 
 #else
 
-void ItbPageFault::invoke(ThreadContext * tc)
+void
+ItbPageFault::invoke(ThreadContext *tc)
 {
     Process *p = tc->getProcessPtr();
-    Addr physaddr;
-    bool success = p->pTable->translate(pc, physaddr);
-    if(!success) {
+    TlbEntry entry;
+    bool success = p->pTable->lookup(pc, entry);
+    if (!success) {
         panic("Tried to execute unmapped address %#x.\n", pc);
     } else {
         VAddr vaddr(pc);
-        VAddr paddr(physaddr);
-
-        TlbEntry entry;
-        entry.tag = vaddr.vpn();
-        entry.ppn = paddr.vpn();
-        entry.xre = 15; //This can be read in all modes.
-        entry.xwe = 1; //This can be written only in kernel mode.
-        entry.asn = p->M5_pid; //Address space number.
-        entry.asma = false; //Only match on this ASN.
-        entry.fonr = false; //Don't fault on read.
-        entry.fonw = false; //Don't fault on write.
-        entry.valid = true; //This entry is valid.
-
         tc->getITBPtr()->insert(vaddr.page(), entry);
     }
 }
 
-void NDtbMissFault::invoke(ThreadContext * tc)
+void
+NDtbMissFault::invoke(ThreadContext *tc)
 {
     Process *p = tc->getProcessPtr();
-    Addr physaddr;
-    bool success = p->pTable->translate(vaddr, physaddr);
-    if(!success) {
+    TlbEntry entry;
+    bool success = p->pTable->lookup(vaddr, entry);
+    if (!success) {
         p->checkAndAllocNextPage(vaddr);
-        success = p->pTable->translate(vaddr, physaddr);
+        success = p->pTable->lookup(vaddr, entry);
     }
-    if(!success) {
+    if (!success) {
         panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
     } else {
-        VAddr paddr(physaddr);
-
-        TlbEntry entry;
-        entry.tag = vaddr.vpn();
-        entry.ppn = paddr.vpn();
-        entry.xre = 15; //This can be read in all modes.
-        entry.xwe = 15; //This can be written in all modes.
-        entry.asn = p->M5_pid; //Address space number.
-        entry.asma = false; //Only match on this ASN.
-        entry.fonr = false; //Don't fault on read.
-        entry.fonw = false; //Don't fault on write.
-        entry.valid = true; //This entry is valid.
-
         tc->getDTBPtr()->insert(vaddr.page(), entry);
     }
 }