ARM: Decode neon memory instructions.

[gem5.git] / src / arch / alpha / interrupts.hh

diff --git a/src/arch/alpha/interrupts.hh b/src/arch/alpha/interrupts.hh
index abfecfb5bed8a0483569f773f3acb7972bcac527..3200201dbed3210e0b36b7448be857376cbae673 100644 (file)
--- a/src/arch/alpha/interrupts.hh
+++ b/src/arch/alpha/interrupts.hh
@@ -35,29 +35,47 @@
 #include "arch/alpha/faults.hh"
 #include "arch/alpha/isa_traits.hh"
 #include "base/compiler.hh"
+#include "base/trace.hh"
 #include "cpu/thread_context.hh"
+#include "params/AlphaInterrupts.hh"
+#include "sim/sim_object.hh"
 
 namespace AlphaISA {
 
-class Interrupts
+class Interrupts : public SimObject
 {
   private:
     bool newInfoSet;
     int newIpl;
     int newSummary;
+    BaseCPU * cpu;
 
   protected:
     uint64_t interrupts[NumInterruptLevels];
     uint64_t intstatus;
 
   public:
-    Interrupts()
+    typedef AlphaInterruptsParams Params;
+
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+
+    Interrupts(Params * p) : SimObject(p), cpu(NULL)
     {
         memset(interrupts, 0, sizeof(interrupts));
         intstatus = 0;
         newInfoSet = false;
     }
 
+    void
+    setCPU(BaseCPU * _cpu)
+    {
+        cpu = _cpu;
+    }
+
     void
     post(int int_num, int index)
     {
@@ -90,7 +108,7 @@ class Interrupts
     }
 
     void
-    clear_all()
+    clearAll()
     {
         DPRINTF(Interrupt, "Interrupts all cleared\n");
 
@@ -113,7 +131,7 @@ class Interrupts
     }
 
     bool
-    check_interrupts(ThreadContext *tc) const
+    checkInterrupts(ThreadContext *tc) const
     {
         return (intstatus != 0) && !(tc->readPC() & 0x3);
     }
@@ -121,14 +139,14 @@ class Interrupts
     Fault
     getInterrupt(ThreadContext *tc)
     {
-        int ipl = 0;
-        int summary = 0;
+        uint64_t ipl = 0;
+        uint64_t summary = 0;
 
         if (tc->readMiscRegNoEffect(IPR_ASTRR))
             panic("asynchronous traps not implemented\n");
 
         if (tc->readMiscRegNoEffect(IPR_SIRR)) {
-            for (int i = INTLEVEL_SOFTWARE_MIN;
+            for (uint64_t i = INTLEVEL_SOFTWARE_MIN;
                  i < INTLEVEL_SOFTWARE_MAX; i++) {
                 if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
                     // See table 4-19 of 21164 hardware reference
@@ -140,7 +158,7 @@ class Interrupts
 
         uint64_t interrupts = intstatus;
         if (interrupts) {
-            for (int i = INTLEVEL_EXTERNAL_MIN;
+            for (uint64_t i = INTLEVEL_EXTERNAL_MIN;
                  i < INTLEVEL_EXTERNAL_MAX; i++) {
                 if (interrupts & (ULL(1) << i)) {
                     // See table 4-19 of 21164 hardware reference
@@ -171,13 +189,6 @@ class Interrupts
         tc->setMiscRegNoEffect(IPR_INTID, newIpl);
         newInfoSet = false;
     }
-
-    uint64_t
-    get_vec(int int_num)
-    {
-        panic("Shouldn't be called for Alpha\n");
-        M5_DUMMY_RETURN;
-    }
 };
 
 } // namespace AlphaISA